Hi,
I have a design written in VHDL that I wish to insert in between two verilog sub modules.
I’ve followed the previous topic written on here on how to instantiate the component inside a verilog module here. Instantiating VHDL Components in Verilog Modules
This works all fine and dandy.
However, my case is a little more complex. The two verilog sub modules contain reg output ports that connects to an input signal port of the next module. When I instantiate my component in between them, I have no trouble mapping the signals together and did view them in RTL Elaboration in Quartus II, but I’m not seeing any signal changes using SignalTap II (Quartus II). There is no direct REG to signal mapping for VHDL ? A REG statement, as I’ve researched is just a signal assigned at the transition of another signal, causing storage to be allocated by the compiler. I’m not familiar with Verilog. Is there another way I can map this signal as in using wire statment or a dummy module that simply maps in to out so I can just use the wire as a mapping function to instantiate my VHDL component?
Hello ubsanders,
I’m not familiar with the programming issues. Hopefully one of the engineers are familiar with this setup, and can help you with this problem.
Helo ubsanders,
Yes, a Verilog reg is like the D output of a flip flop.
As I understand your question, the Verilog modules feature registered outputs something like this:
output reg PWM,
output reg [B - 1:0] cnt
You are able to connect the modules and successfully synthesize the project without error. However, the sniffer tools are unable to see the signals.
As always, I would recommend checking the warnings. I can’t tell you how many times the synthesis tools have optimized away my blocks due to some silly error.
If necessary, you could modify your Verilog modules to use wires. This would require the registers to be moved inside the block. It would also require an assign operator to copy the registers to the output wire. I could be mistaken, but I don’t think this is necessary as all outside connection to the Verilog module are wires; internally it’s like looking at the D output, externally, wires connect modules.
One final thought, you mentioned submodules within a design hierarchy. Is it possible that the SignalTap tool does not have access to the underlying wires. For example, it’s possible synthesizer optimization has removed the wires. Perhaps you could make the wires “global” by extending them through your top block. With this change there will be continuity from the top level of your program all the way to the wires of interest in your sub or sub-sub modules.
Sorry I cannot provide further (timely) assistance as my background is Xilinx and Verilog.
Best Wishes,
APDahlen
P.S. If this does not answer your question, please post on a new thread and include your RTL code.
