This site provides many VHDL components for use. Modern FPGA synthesis software allows mixed language designs, so all of these components work in Verilog designs as well as VHDL.
Instantiating a VDHL component in a Verilog module is very straightforward, as it follows exactly the same syntax as instantiating Verilog modules themselves:
<vhdl_component_name> # ( <generic_values_list> ) <instance_name> ( <port_map_list> );
Here is an example design that instantiates a VHDL component in a top-level Verilog module. The design debounces two buttons by instantiating this debounce VHDL component twice. The entity code of the VHDL component is shown here:
ENTITY debounce IS GENERIC( clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz stable_time : INTEGER := 10); --time button must remain stable in ms PORT( clk : IN STD_LOGIC; --input clock reset_n : IN STD_LOGIC; --asynchronous active low reset button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce;
To instantiate this VHDL component in Verilog, simply declare the component and map the generic parameters and ports to the corresponding parameters and ports in the Verilog module, using standard Verilog syntax. The example Verilog code below infers the mapping based on the order the parameters and ports are listed. 50_000_000 is mapped to the clk_freq generic, 10 is mapped to the stable_time generic, and the Verilog ports listed are mapped to the VHDL ports in the order that the VHDL ports are declared in the component’s entity.
module verilog_debounce( input clk, //system clock input reset_n, //asynchronous active low reset input [1:0] button, //two input signals to be debounced output [1:0] result //two debounced signals ); debounce #(50_000_000,10) //VHDL component name and generic parameter mapping debounce_0(clk,reset_n,button,result); //instance name and port mapping for first signal debounce #(50_000_000,10) //VHDL component name and generic parameter mapping debounce_1(clk,reset_n,button,result); //instance name and port mapping for second signal endmodule
All other Verilog syntax and functionality also applies. As such, the mapping can instead be done explicitly (listing both the Verilog and VHDL ports). Generate statements can create multiple instantiations of the same component, and etc.
Mixed language design is a great asset for digital designers. It significantly increases the library of IP cores available.