PS/2 Keyboard Interface Logic: ps2_keyboard.vhd (5.1 KB)
Debounce Logic (must also be included in the project): debounce.vhd (2.4 KB)
- VHDL source code of a PS/2 keyboard interface
- Outputs the PS/2 make and break codes received from a keyboard
- Sets flag output when new code is available
- Validates parity, start, and stop bits of PS/2 transactions
- Configurable system clock frequency
- Synchronizes between PS/2 and system clock domains
- Debounces incoming PS/2 signals
This details a PS/2 keyboard interface component for use in CPLDs and FPGAs, written in VHDL. The component receives data transactions from a PS/2 keyboard and provides the keyboard make and break codes to user logic over a parallel interface. It was designed using Quartus II, version 12.1. Figure 1 illustrates a typical example of the PS/2 keyboard interface integrated into a system. An example design that implements this PS/2 keyboard interface component to make a PS/2 keyboard to ASCII converter is available here. The PS/2 keyboard interface is itself a simplified version of the PS/2 Host Transceiver available here.
Figure 1. Example Implementation
PS/2 (IBM Personal System/2) is an interface for keyboards and mice to PC compatible computer systems via a 6-pin Mini-DIN connector. The computing system must provide the keyboard or mouse with 5V source and ground connections. Communication occurs over a 2-wire serial interface, consisting of a clock line and a data line. Both lines require pull-up resistors (2kΩ shown in Figure 1). The 120Ω series resistors in Figure 1 are required to interface the 3.3V FPGA I/O to the 5V signals.
Once powered, the keyboard goes through a self- initialization sequence. Upon completion, it is ready to communicate keyboard events over the PS/2 interface.
Figure 2 illustrates the transaction format. Both clock and data signals are logic level high when inactive. The keyboard provides both the clock and data. The clock has a frequency between 10 kHz and 16.7 kHz (i.e. a 60-100us period). The data begins with a start bit (logic low), followed by one byte of data, a parity bit, and finally a stop bit (logic high). The data is sent LSB first. Each bit should be read on the falling edge of the clock signal. Once complete, both the clock and data signals return to logic level high.
Figure 2. PS/2 Keyboard Transmission Timing Diagram
The data byte represents part of a keyboard scan code: either a make code (key press) or a break code (key release). Three different sets of scan codes exist, however the vast majority of keyboards use Scan Code Set 2, which is provided in the Appendix. A make code usually consists of either one or two bytes. If a make code uses two bytes, the first byte is x“E0”. A given key’s break code is typically the same as its make code, except that break codes include an additional x“F0” byte as the 2nd to last byte. (The PAUSE and PRNT SCRN keys are exceptions to the above.)
While it is possible to send data to a keyboard (to change its settings, etc.), this is generally unnecessary and is not included in this VHDL component. However, the PS/2 Host Transceiver component available here can be used to do this.
Figure 3 conceptually illustrates the PS/2 keyboard interface component’s architecture. The clock and data signals from the keyboard are first synchronized and debounced. (The debounce component VHDL is provided above and documentation is available here.) The resultant internal PS/2 data signal is then serially loaded into a shift register on falling edges of the PS/2 clock. An idle counter determines when the transaction is finished, defined by the PS/2 clock remaining at a high logic level for more than 55us, i.e. longer than half of the worst-case PS/2 clock period. Combinational error checking logic verifies the start bit, stop bit, and parity bit with the data. When the PS/2 port is idle and the data is valid, the component outputs the received PS/2 code and sets the ps2_code_new signal high to indicate that a new code is available on the ps2_code bus. The code remains available on the bus until another code is received. The ps2_code_new signal remains high until another PS/2 transaction begins (when a low PS/2 clock signal clears the idle counter).
Figure 3. PS/2 Keyboard Interface Logic Architecture
Table 1 describes the PS/2 keyboard interface’s ports.
Table 1. Port Descriptions
The system clock speed affects the debounce time and the idle counter timing. The two GENERIC parameters declared in the ENTITY, clk_freq and debounce_counter_size must be set appropriately for the component to operate correctly. The clk_freq parameter must be set to the system clock clk frequency in Hz. The default setting in the provided code is 50 MHz (the frequency at which the component was simulated and tested). The debounce_counter_size parameter must be set such that 2^debounce_counter_size / clk_freq = 5us, as described in the documentation for the debounce component here. For a 50 MHz system clock, debounce_counter_size = 8.
Figure 4 shows the timing diagram of an example transaction. Once the PS/2 clock signal goes low, the ps2_code_new flag deasserts to indicate that a new PS/2 keyboard transaction is in progress. When the transaction completes, the ps2_code_new flag asserts to indicate that a new PS/2 code has been received and is available on the ps2_code bus. In this case, the PS/2 code received is x“1C”, which is the make code for the “A” key.
Figure 4. Example PS/2 Transaction
This PS/2 keyboard interface is a programmable logic component that receives transactions from PS/2 keyboards. It synchronizes the clocks domains, debounces the input signals, performs error checking, and notifies the user logic when new codes from the keyboard are available on its parallel output bus.
Table A1. Keyboard Scan Code Set 2
|Key||Make Code||Break Code|
Comments, feedback, and questions can be sent to firstname.lastname@example.org.