In embedded systems, timers are critical peripheral modules. They are used not only for precise delays but also for generating Pulse Width Modulation (PWM) signals, capturing external events, and executing periodic tasks.
In our previous post in this series on timers, Introduction to AVR Microcontroller Timer TCA Modes, we went over AVR TCA timer modules. This post continues with another common timer operation mode:
Timer (TCD)
TCD is a 12-bit timer optimized for generating complex PWM waveforms (e.g., half-bridge and full-bridge outputs). It is available in devices such as the tinyAVR® 1-series and AVR® DA Family.
There are two comparators inside the TCD: CMPA and CMPB. Each comparator has a set (SET) value and a clear (CLR) value. When the timer value reaches the set value, the output becomes active; when it reaches the clear value, the output becomes inactive.
The TCD supports four operating modes: single-ramp mode, dual-ramp mode, quad-ramp mode, and dual-slope mode. These names indicate the number of cycles the timer goes through. In quad-ramp mode, it goes through four cycles and resets successively at CMPASET, CMPACLR, CMPBSET, and CMPBCLR; in dual-ramp mode, it goes through two cycles and resets successively at CMPACLR and CMPBCLR; in single-ramp mode, it resets only at CMPBCLR; finally, in dual-slope mode, the timer counts up to CMPBCLR first and then counts down to zero. For the sake of intuitive understanding, in the following diagram, the endpoints of each ramp are at the same position on the y-axis; however, when the relevant values are not equal, the actual situation will be different. Additionally, the values not shown (such as CMPASET in single-ramp mode) are still valid, but they do not play a role in the cycle.
Figure 4: TCD Operation Modes
Through the Event System , TCD supports input blanking, digital filtering, and various additional modes to clear outputs and/or pause counting. It also enables input capture. Additionally, TCD can operate with a Phase-Locked Loop (PLL) for frequencies higher than the main clock.
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