J-link Interface - JTAG Interface Connection

J-Link supports multiple target Interfaces. Currently, the following interfaces are supported:

  • JTAG
  • cJTAG
  • FINE
  • SPD
  • ICSP

One common interface example is JTAG. The JTAG Interface Connection is a 20-pin system, as below.


*On later J-Link products like the J-Link ULTRA+, these pins are reserved for firmware extension purposes. They can be left open or connected to GND in a normal debug environment. They are not essential for JTAG/SWD in general.

J-Link has a JTAG connector compatible to ARM’s Multi-ICE. The JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54mm male) that mates with IDC sockets mounted on a ribbon cable. To be able to make the correct connection, it is necessary to check the JTAG pinout carefully.

The following shows the J-Link JTAG pinout:

Pin Signal Type Description Function
1 VTref Input Target Reference Voltage It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.
2 Not connected NC Not connected in J-Link It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.
3 nTRST Output JTAG Reset Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
5 TDI Output JTAG data input of target CPU It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of target CPU.
7 TMS Output JTAG mode set input of target CPU This pin should be pulled up on the target. Typically connected to TMS of target CPU.
9 TCK Output JTAG clock signal to target CPU It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.
11 RTCK Input Return test clock signal from the target Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
13 TDO Input JTAG data output from target CPU Typically connected to TDO of target CPU.
15 nRESET I/O Target CPU reset signal Typically connected to the RESET pin of the target CPU, which is typically called “nRST”, “nRESET” or “RESET”. This signal is an active low signal.
17 DBGRQ NC Not connected inside J-Link It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
19 5V-Supply Output Supply Voltage This pin can be used to supply power to the target hardware.


  • All pins marked NC are not connected inside J-Link. Any signal can be applied here; J-Link will simply ignore such a signal. Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

  • Pin 2 is not connected inside J-Link. A lot of targets have pin 1 and pin 2 connected. Some targets use pin 2 instead of pin 1 to supply VCC. These targets will not work with J-Link, unless Pin 1 and Pin 2 are connected on the target’s JTAG connector.

  • Pin 3 (TRST) should be connected to target CPUs TRST pin (sometimes called NTRST). J-Link will also work if this pin is not connected, but you may experience some limitations when debugging. TRST should be separate from the CPU Reset (pin 15)

  • Pin 11 (RTCK) should be connected to RTCK if available, otherwise to GND.

  • Pin 19 (5V-Target supply) of the connector can be used to supply power to the target hardware. Supply voltage is 5V, max. current is 300mA. The output current is monitored and protected against overload and short-circuit.

To learn more J-Link interface , please visit “Segger J-Link interface description”.