Hello Steve, Hello Rolf,
Thanks a lot for the prompt replies. Sorry to come back late as I was out of office. The links shown are subLVDS to CSI2.
Could you please indicate document capturing plain LVDS to CSI2.
Basically I wanted to know, DDR data transfer protocol interface. Our sensor interface is shown above with bit_clk (lvds clk), frame_clk indicating valid 10 bit data clock and lvds_data_valid signal to indicate the complete line data (total data for every line=3203220bits converted to 10bit raw sample). Outside valid data, plan is to send the sync/idle data.
It would be helpful, if you could share the detailed protocol interface for the LVDS RX interface. Thanks a lot for your support.
If possible for a call to discuss by some means, that would really help.