Low frequency ADC eval board

We are currently evaluating analog-to-digital converters (ADC). Having a relatively low sample rate of 10MSPS. We need these ADCs to operate on input frequencies down to D.C or at least down to 500kHz. Although the many chips support operation going down to D.C., all the evaluation boards we’ve seen so far don’t go below 1MHz (most only to 5MHz). Any ideas?

Hello markatmerlintps - welcome to the Forum community! I wasn’t sure of an answer for your question so I checked with others. One of our Product Managers had these suggestions for you: “I would start my search with SAR… successive approximation.Register… because those are normally slower innately.” These are SARs I located in my search. Further, he suggessted “higher precision products such as the sigma delta converter AD7768, goes from DC to 110.8 kHZ could also be an option. EVAL-AD7768FMCZ you may want to check it out.”

Hello markatmerlintps,

Finding an ADC solution in the10 Msps performance category is no easy task.

Assuming you are from academia, an answer may already be on campus in one of the Electrical Engineer Radio Frequency labs.

  1. Perhaps you have an oscilloscope with an Ethernet connection. It’s possible that such a device could feed the raw ADC data directly to your PC for processing. You are on the edge, but it might just work. It would take some exploration of the user and programming manuals for the instruments. If the instrument doesn’t stream the data, you may be able to batch process in a meaningful way especially if the oscilloscope has a deep memory.

  2. Devices such as the Digilent Discovery Pro may be able to perform the operation. Recommend you consult their technical team to determine of a scripting operation could be used to stream or batch process the data.

  3. Any number of raw ADCs could do the job. However, such things typically require an FPGA to process the data. An example is this ZMOD board. As a point of reference, devices such as the Discovery pre-packaged one or more high-performance ADCs, an FPGA, and a high-speed interface to your PC.

  4. It’s possible that a high-end microcontroller or DSP would be up to the task. You would likely need to coordinate Direct Memory Access (DMA) features to make this work. Again, you are up against the edge of performance.

  5. The last item to consider is the ETTUS USRP platform. Again, you may already have such a unit on campus:

with daughter card suitable for DC to 30 MHz:

This is a software defined radio system. Think of it as a high-speed ADC on the of a USB cable. As for software, among others, it connects to GNU radio which is programmed in a graphical language. There are many tools for signal processing. In fact, I’ve used in some of my classes with non-engineering students to construct audio filters - very easy to do. In the hands of a skilled engineer the combination is like magic.

Welcome to the forum.

Kindly let us know how you solved the problem. Your response could help our future readers.

Best Wishes,



Welcome to the forum.

The issue is the input circuitry feeding the ADC. It’s very difficult, and expensive, to accurately pass through/condition both radio frequencies and low frequencies down to DC. So evaluation boards usually only do one or the other, not both.


Thank you, Paul.

If we had a board that passes through just the AM band, that would enable us to pilot our first grade of service. Know of any?

Hello markatmerlintps,

Please tell us know more about your constraints:

  1. system type e.g., PC vs embedded

  2. interface type e.g., high level USB vs a low-level soldered device

  3. level of expertise your team has with microcontrollers and FPGA platforms

  4. ADC interface type: serial (SPI or QSPI) vs parallel

  5. ADC bit depth

  6. Nyquest f_max (assumed 4 MHz at this point)

Thank you,




Thank you.

I could use two boards, one doing <1MHz and the other >5MHz

Do you know of a board or of a source I can check for a board/box that operates below 1MHz?

Many test equipment manufacturers have products to do what you need (e.g. the Digilent Discovery Pro linked above), but I don’t know of any ADC IC manufacturers who offer evaluation boards with test equipment level specs.

1 Like


Thanks so much for all your information so far.
The jouney continues.

Please let us know more about your constraints:

  1. system type e.g., PC vs embedded embedded

  2. interface type e.g., high level USB vs a low-level soldered device low-level soldered device

  3. level of expertise your team has with microcontrollers and FPGA platforms High

  4. ADC interface type: serial (SPI or QSPI) vs parallel either

  5. ADC bit depth prefer 14 but 16 OK

  6. Nyquest f_max (assumed 4 MHz at this point) That;s fine

Hello markatmerlintps,

Those requirements and capabilities place you somewhere near products such as this:

A good deal of processing can be done with the FPGA and the dual-core embedded Arm processor. Please see the Diligent page for additional option included hardware bundles and module options.

Once again, I would encourage you to consider the options in my previous note. The prebuilt devices with associated software may allow you to save time in the prototype stage. Also, there is a higher chance the hardware may be reused especially in an (assumed) academic environment.

Best Wishes,


P.S. See also this ADC Selector Guide. You may be able to find other demo boards. However, most devices in this performance category are designed to connect to a FPGA board.

Thank you very much, APDahlen,
I appreciate your time.

I will look at these right away.
We are planning on use of an FPGA board as well.
Although along with use of a softcore.

If you have any opinions about a softcore I’d sure like to hear it.

We are a little bit leery of ARM

This is not an academic environment. For both commercial and military environments. And so it must be made in the U.S.

The short story is this. We have a functional (not production) prototype based on a USRP (with daughter board) and other gear.
We want to build a subsequent prototype that is more consolidated, yet we want to use ready-made boards to get pilots up and running as soon as possible.
After this subsequent prototype for pilots, we will work with an ODM to fabricate a custom RF front-end card (we have broader requirements) combined with an FPGA and we assume softcore.

This is a system to replace/augment the current GPS system. (www.merlintps.com) Our biggest hurdle currently is we want to improve our response time from 10 seconds to 1 second. It’s SDR based. Some of the functions of the SDR will need to be FPGA-based (e.g. as hw accelerators or custom instructions).

PLEASE NOTE: The ADC3643EVM board meets all our qualifications for an RF card except we don’t see support for an external trigger. Can you confirm for us please?

If we find the right card like this one (including it’s price) we are targeting ordering 10s of these in 2024. And when we go to production the quantity of chips would be in the millions.

I have been looking at everything you sent. And discussing with our chief scientist as applicable.

Here’s our other requirements:

  • 10MSPS (higher OK but mind the I/O speed required)

  • Need external clock input. Minimum 10MHz

  • Need external trigger for 1 second samples

  • SPI control interface

  • LVDS interface for samples (high speed serial)

  • 14-bit (although 16-bit OK)

  • Jitter should be in fempto-seconds. Or listed as 0.1 pico-seconds.

  • Noise floor should be around 72-73dB

  • Spurious responses ~88dB

  • Power supply 1.8V. Although could be fed by 5V supply

  • SPI interface for support of USB interface (not a hard requirement)

  • Input frequency bandwidth down to 500kHz (or D.C. if possible)


So close!

That board meets all our criteria except 1. External trigger.

Can you double check for me, please, that it does or does not have an external trigger?

Hello markatmerlintps,

Thank you, I have a much better understanding of your situation. You have a working USRP model and desire to shift to a production. As I understand, you have commissioned a suitable RF front end and are working on the SDR pieces such as the digitizer and various algorithms.

Let me start by saying you are outside of my expertise. At the same time, this sound very much like my previous PNT work with the eLORAN system and precision timing. Ref: 2446.pdf (nist.gov) and ADA503340.pdf (dtic.mil). With that said, I may be able to provide some divergent ideas for your consideration:

If you aren’t too far into the design process, your contractor may be able to integrate the ADC into the RF daughterboard. As an example, consider the PCB shown at the end of this note. The board is based on the older ADC14L020CIVY ADC. It’s a 14-bit device capable of 20 MSPS. The PCB design is not pretty and violates many design rules. However, it did work and was able to digitize the DGPS signal. As a side note, this older ADC meets many of your design requirements. Know that many new high-performance ADC have been produced in the 18 years since it was first produced.

Careful integration of the RF front end and ADC is essential. This would include and appropriate voltage reference, and perhaps more importantly, bandwidth appropriate attenuators and the low-pass Nyquist filter.

As I recall, the ADC itself wasn’t much of a problem. Rather, the physical connections to the FPGA board (Digilent GENESYS) were much more challenging. In this case, I used a parallel connection with registered outputs. As I recall, one clock signal would activate the ADC while another activated an octal latch. A third clock - synchronous with the first - would then transfer the data into the FPGA. Perhaps not ideal, and certainly overdesigned, but it was a safe design decision for a board I could scarcely afford to design once.

Trigger options

I’m not sure what is implied with the term trigger as it relates to your sampled system. Specifically, is the trigger an ADC function or is it an FPGA function?

One solution is to run the ADC continuously at the normal sample rate. The samples are then placed into a large FPGA memory. In a FPGA triggered system, start storing samples at memory index zero upon receipt of the trigger. Alternatively, if the FPGA has a large memory, let the trigger capture the index of the ring buffer.

PPS options

As I understand, you are seeking to incorporate PPS timing into this device.

Have you considered adding an OCXO or optional rubidium clock? Instead of bringing the PPS into the FPGA, bring in the quality 1 or 10 MHz signal and then construct a PLL. One crude way to do this is to instantiate a DDS using the high-speed FPGA clock. You then “steer” the DDS to maintain a phase relationship with the quality oscillator. It’s not ideal, but it allows you to discipline the FPGA to the quality oscillator. The trigger can be derived from the DDS or calculated from the high-speed clock.

Also, if there is a PPS signal such as one derived from a GPS receiver, measure the time interval between the received GPS PPS and DDS maintained PPS. Steer the DDS to maintain a zero average error between the PPS signals. The advantage of this technique is that you have effectively locked the OCXO or rubidium-based DDS to the external PPS with the ability to carry over when the GPS PPS signal is lost.

ADC and FPGA selection

Selecting a particular ADC demo board is a circular decision closely tied to the FPGA board which in turn is closely associated with the microcontroller decision. Unfortunately, I am unable to offer any further advice due to the circular nature of the ADC / FPGA decision. Perhaps is you settle on particular FPGA with a particular socket, we may be able to locate a suitable digitizer.

My sincere hope is that you find something useful in this long note.

Best Wishes,




I am so appreciative of your attention to this.

There are two steps to our current efforts.

First, The current USRP implementation must be commanded over Ethernet using the UHD protocol. It takes several seconds for the USRP to lock to the external clock and 1 PPS signal before it can do the capture. We could program the FPGA on board, but there is not a path to do that from the C code we have written - as far as we know. The cost of the USRPs are high, too. About $4K.

This is a GPS alternative. We achieve our processing goal in 10 second updates. In our next prototype, we want to achieve updates in 1 second.

The next first next step is a prototype based on being able to do pilots in the field as soon as possible. We are hoping we can find an off-the-shelf FPGA development board (even if overkill), in combination with an off-the-shelf RF card, that meets our required specifications, which I shared with you. Where we are having trouble is finding an RF card that operates down to 500kHz - to -1710kHz input frequency range. Or in another case supporting the target frequency range, but not a 10MHz external clock and/or an external trigger.

Once these pilots are in the field, we can firm up our production specifications, and then will look to work with an ODM to develop a combined board that efficiently meets our specifications (Second next step).

I can only thank you again for your time and expertise.
Your dialog below is a bit over my head, so I’m going to share with our chief scientist and get back to you.
I guess my question to you for now, is the component and board you’ve discussed below available today?


Where are you located?

Yes, Mark, the Digilent product is available today. Be sure to verify that it has the desired daughtercards. As I recall, there are two slots. You will need to select the configuration most suited for your application.

A GPS alternative is not a trivial application.

The precision timing and resulting position can be held for a few hours upon loss of GPS. Long term stability measured in weeks or even months requires a considerable hardware investment. That was some of my work mentioned in the previous dtic.mil paper. In that paper, I showed how a clock composed of an ensemble of three 5071A cesium time clocks could hold ±50 ns phase error for up to 70 days. Stated another way, I sympathize with the technical mountain you are climbing.

If you have not already done so, may I recommend your team reach out to the eLoran team including Stanford’s Sherman Lo and UrsaNav’s Charles A. Schue. I suspect your work overlaps by a considerable degree.

As requested, my bio is attached below.



P.S. Have you considered using the second ADC channel as the PPS trigger input? As an example, consider this a two-step process - that is assuming your oscillator has both PPS and 1 MHz sinusoidal output.

  1. Send the PPS to the FPGA’s digital input pin using an appropriate level shifting buffer.

  2. Send the 1 MHz signal to an oscilloscope like (ADC) input.

On receipt of the PPS, look for the next 1 MHz zero crossing. Interpolate the samples based on your know sample time. The result has sub nano second accuracy. You will be concerned with things like matching the PPS and 1 MHz cable length.

About the author

Aaron Dahlen, LCDR USCG (Ret.), serves as an application engineer at DigiKey. He has a unique electronics and automation foundation built over a 27-year military career as a technician and engineer which was further enhanced by 12 years of teaching (interwoven). With an MSEE degree from Minnesota State University, Mankato, Dahlen has taught in an ABET accredited EE program, served as the program coordinator for an EET program, and taught component-level repair to military electronics technicians. Dahlen has returned to his Northern Minnesota home and thoroughly enjoys researching and writing articles such as this. LinkedIn | Aaron Dahlen - Application Engineer - DigiKey

1 Like

Aaron, I am reviewing several of the suggestions you sent currently. We did speak with Lombardi of NIST almost 2 years ago where he made us aware of the LSU, NJ, and Stanford efforts. Jonas is an adjunct professor at Stanford and is our Timing business strategist. Ironically the Obama administration demolished most of the Loran towers and UrsaNav and Harris L3 are sugg looking to rebuild them. We will be glad to take advantage of their signals of opportunity when back online.

A good summary of where eLoran sits, by Dana Goward.

1 Like

It’s a small world!

I sincerely wish you every success in strengthening this aspect of our nation’s critical PNT infrastructure.

Let us know if DigiKey can assist in the future. On a personal note, DM if there is need of my limited services as I was once involved in the eLORAN including hardware and the defining specifications - not to conflict with my DigiKey responsibilities.




We have you on our list or resources. And I’ll keep you posted.
Thanks for your above-and-beyond effort so far.

1 Like

I hope you’re having a good week. You suggested the DC14L020. I’ve looked through the two different datasheets and the user’s guide. I can’t confirm if the chip or the eval board will work down to 500kHz analog input frequency.
I can’t get the TI login to go through for me. Do you have a contact at TI that either you or I could contact to confirm the analog input frequency range of the eval board?
Also, the boards you sent pictures of in the forum, might there be a source for those to be purchased today?
For the datasheets, I haven’t reviewed all the graphs, but if one would show the graph with input frequency down to D.C., can I take that literally that the chip/board support input frequency range down that low?