The purpose of this article is to illustrate how to work with the Microchip Configuration Logic Blocks (CLB) shown here,
using the VERYVERILOG MINI FPGA KIT in the MPLAB IDE,
Please download the following project to your directory of preference. Open the project using MPLAB IDE. The VERYVERILOG MINI FPGA KIT will be used in this demo where an LED will be blinked from an internal program, and at the same time, a Verilog module for an independent simple AND gate is implemented in the CLB. The main.c source program is as follows,
#include "mcc_generated_files/system/system.h"
/*
Main application
*/
int main(void)
{
SYSTEM_Initialize();
while(1)
{
CLBSWINL = 0; // starts with digit "0"
for(uint8_t counter = 0x00; counter <= 0x0F; counter++) // loop for incrementing between 0h and Fh
{
__delay_ms(1000); // waits until displays
CLBSWINL = CLBSWINL + 1; // increments the displayed hexadecimal number
}
}
}
This program was originally designed to control a classical old school 7 segment display, but was simplified to illustrate a very basic CLB example, for introductory purposes. The main.c initializes all these,
void SYSTEM_Initialize(void)
{
CLOCK_Initialize();
CLB1_Initialize();
PIN_MANAGER_Initialize();
CRC_Initialize();
INTERRUPT_Initialize();
}
Then it proceeds to increment a counter where one of the bits will be used to toggle an LED.
Now, from the MPLAB IDE in this project, please navigate to the Windows → MPLAB Code Configurator menu. From the Application Builder select the Application Builder as shown below, specifically click the CLB1 box,
Then the CLB synthesizer Library will appear as shown below,
Here we have created a direct connection of the CLBSWIN0 variable controlled periodically in the main.c source program via the CLB to the PPS_OUT1 port (mapped to an LED). Also an AND gate module is implemented in Verilog. This andgate Verilog module is connected to the CLBIN1PPS and CLBIN3PPS to the independent inputs (a,b) (mapped to two push buttons in the dev kit) and the output is connected to the PPS_OUT2 (to an output LED in the dev kit). If this Verilog module is double clicked in the block diagram, then the AND gate Verilog code is displayed as shown below,
If any change is applied to the CLB design itself the developer has to click the Synthesize button again (To create a new clbBitstream.S file in the project) before a new build is created and downloaded to the Microchip PIC16F13145. Also in the PIN Package View as shown below with the proper PIN assignment were made for this simple demo in the VERYVERILOG MINI FPGA KIT using the corresponding schematic,
and as shown here,
Now from the MPLAB IDE build it,
BUILD SUCCESSFUL (total time: 6s)
and program the Microchip PIC16F13145 in the VERYVERILOG MINI FPGA KIT.
If its programmed successfully then CLB demo will run as shown in the next video,
The PPS_OUT1 port is connected to one of the platform LEDs and it is properly blinking periodically from the main.c. Also the AND gate output is connected to two input switches and to another indenpedent LED at the output. From this video this CLB demo is working properly. The basic CLB demo for the VERYVERILOG MINI FPGA KIT is complete.
The VERYVERILOG MINI FPGA KIT is a very simple development kit that can be used from the MPLAB IDE as well as from the internet too for the CLB part. There are online tools like this one veryVerilog - Logic Circuit Design 101 - Microchip Try that will allow the developer to create a CLB file and that can be synthesized to as .S file in a project where it is imported in the MPLAB IDE (for building it) and download via the IDE itself or can be downloaded via the WebICSP v1.8. The VERYVERILOG MINI FPGA KIT is a very easy to use platform for beginners and novices who want to learn more about CLBs and is available at DigiKey!
Have a wonderful day!






