Microchip MIC24066 Buck Power Supply Design: Key Waveform Analysis During Steady-State Operation

Semiconductor Integrated Circuits (ICs)
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The steady-state operating condition of a Buck power supply is the core scenario where the power supply continuously and stably provides power to the load. Analyzing the key waveforms under steady state is a critical prerequisite for in-depth understanding of the power supply’s control architecture and ensuring design reliability and performance.

We will take the Microchip MIC24066T switching buck regulator as an example.

1. Analysis of Key Waveforms During Steady-State Operation

The figure below shows the key waveforms of the MIC24066/7 series synchronous buck regulator during steady-state operation:

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(Image source: Microchip)

1.1 Inductor Current ( IL)

  • Waveform Shape: Sawtooth wave, reflecting the current change of the inductor during the “energy storage - energy release” process.
  • Key Parameters:
    • IOUT: DC component of the load current (under steady state, the average value of the inductor current equals the load current).
    • ΔIL(pp) : Peak-to-peak ripple of the inductor current (the amount of change in current from valley to peak).
  • Physical Significance: When the high-side MOSFET is turned on, the inductor “stores energy” (current rises); when the low-side MOSFET is turned on (for freewheeling), the inductor “releases energy” (current drops). The ripple magnitude is determined by the inductance value, input/output voltage, and switching frequency.

Note: Formula for inductor current ripple:
ΔI_{L(pp)} = \dfrac{(V_{IN} \ - \ V_{OUT}) \times T_{ON}}{L}

1.2 Output Voltage VOUT

  • Waveform Shape: Small sawtooth ripple synchronized with the inductor current ripple.
  • Key Formula: ΔVOUT(pp) = ESR × ΔIL(pp)
    • ESR: Equivalent Series Resistance of the output capacitor.
  • Physical Significance: The output voltage ripple is mainly caused by “the inductor current ripple flowing through the ESR of the output capacitor”. (If a low-ESR ceramic capacitor is used, this ripple will be very small, and additional “ripple injection” design is required — refer to the previous section of the datasheet.)

Note: In most applications with low-ESR ceramic capacitors, capacitor charging/discharging may have a more significant impact than the ESR term.

1.3 Feedback Voltage (VFB)

  • Waveform Shape: In-phase with the output voltage ripple, but its amplitude is reduced by the voltage division of the feedback resistors.
  • Key Formula: ΔVFB(pp) =ΔVOUT(pp) × R2 / (R1+R2)
    • (R1, R2): Feedback voltage-divider resistors (scale down the output voltage proportionally to compare it with the internal 0.6V reference VREF).
  • Physical Significance: The feedback network “samples” the output voltage ripple to the VFB pin, allowing the controller to detect changes in the output voltage. When VFB is lower than VREF, the next conduction cycle is triggered.

1.4 High-Side Drive Signal (DH)

  • Waveform Shape: Periodic square-wave pulses, representing the on-time (TON) of the high-side MOSFET.
  • Estimated On-Time: Pre-calculated based on VIN, VOUT, and switching frequency FSW, with the formula: TON = VOUT /( VIN × FSW).
  • Conduction Trigger Condition: When V_FB is lower than the internal reference V_REF, the next conduction cycle of the high-side MOSFET is triggered immediately.
  • Physical Significance: Core logic of the adaptive on-time control architecture — the on-time is “pre-estimated”, but the off-time is dynamically adjusted by the feedback voltage. If the output voltage drops (VFB falls), conduction is triggered in advance to achieve “fast transient response”.

2. Overall Logic: Steady-State Control Process

  1. High-Side Conduction Phase: The high-side MOSFET is turned on → inductor current rises → output capacitor charges, and VOUT increases slightly → VFB rises synchronously (but remains lower than VREF).
  2. Low-Side Conduction/Freewheeling Phase: The high-side MOSFET is turned off, and the low-side MOSFET is turned on → inductor current drops → output capacitor discharges, and VOUT decreases slightly → VFB drops synchronously.
  3. Trigger New Conduction Cycle: When VFB < VREF, the next high-side conduction cycle is triggered, and the above process repeats.

3. Final Notes

The analysis of key waveforms during steady state in this article ignores the impact of “reactive impedances” such as capacitor reactance and inductor reactance, and only focuses on the effect of “ESR ripple” and “feedback voltage division” on the control logic — this is to facilitate understanding of the key waveforms under steady state. In actual design, it is necessary to optimize the feedback network based on the capacitor type (e.g., low-ESR ceramic capacitors require additional ripple injection) to ensure that the amplitude and phase of the FB ripple meet the trigger requirements.

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