The Microchip PIC is flexible in I/O pin selection, but there are hardware limitations. This brief explores a specific example related to the SPI peripheral with an emphasis on the microcontroller’s Peripheral Pin Select (PPS) Module.
This article dispels the myth that all pins can connect to all peripherals. This is a critical step in microcontroller selection and PCB design. Get this wrong, and you will learn the joys of cutting circuit traces, adding bodge wires, and then adding a revision number to your next PCB.
Getting Started with PIC Pin Assignment
Microchip PIC I/O pin assignments may be manually written into the Special Function Registers (SFRs) or they may be entered via MCC. Figure 1 presents the MCC pin assignments for the SPI peripherals for a QFN40-packaged PIC16F17576.
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MSSP1 allows connections to Ports B and C
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MSSP2 allows connections to Ports B and D
Figure 1: MCC pin assignments for the PIC16F17576 SPI peripheral.
Datasheet Documentation of I/O Pin Assignments
The pin assignments are contained within the PPS Input Selection Table and the PPS Output Selection Table. An example is included as Figure 2. The SDO2 output source is highlighted. For the 40-pin devices, the table shows routing to Ports B and D. Likewise, the SDO1 signal shows Ports B and C. This is identical to the MCC representation shown in Figure 1.
Figure 2: PPS Output Selection Table for the PIC16F17576 with SDO2 highlighted.
Discovering the Peripheral Pin Select (PPS) Module
Figure 3 presents the block diagram for the microcontroller’s PPS. In its simplest form, it consists of two parts:
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Input side: A multiplexer accepts multiple I/O pin inputs. A PPS SFR determines which physical input signal is routed to the peripheral.
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Output side: A multiplexer is associated with each I/O pin. A PPS SFR determine which peripheral signal is routed to a physical output pin.
For the SPI hardware configured as a master, we require one input multiplexer for MISO signal and two output multiplexers for the MOSI and SCK signals. The active-low CS_NOT signal is handled through a GPIO pin assignment.
Figure 3: Block diagram of the PPS.
Multiplexer Limitation
The PPS Input Selection Table and the PPS Output Selection Table may be used to infer the number and size of the multiplexers. Assuming a PIC16F17576:
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If all input pins were exposed, we would need a 36-input multiplexer. The quantity of multiplexers is determined by the number of peripherals.
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If all output pins were exposed, we would need a total of 36 multiplexers. The input width of each multiplexer is determined by the total number of peripheral output signals.
Taken together, this would consume considerable silicon. Timing constraints and layout complexity would increase. As an analogy, consider PCB design. Doubling the number of nets does not double the effort. Instead, each wire must be considered in relationship to every other wire. The microcontroller designers would face a similar non-linear routing problem. Based on these observations, we can safely assume that the designers struck a balance between cost and flexibility.
Parting Thoughts
Wouldn’t it be fun to be a fly on the wall and listen to the PIC engineers discuss the constraints? Then again, you will have a similar conversation as you design a PCB for the PIC.
Sincerely,
APDahlen
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About This Author
Aaron Dahlen, LCDR USCG (Ret.), is a Senior Applications Engineer at DigiKey in Thief River Falls. His background in electronics and industrial automation was shaped by a 27-year military career as both technician and engineer, followed by over a decade of teaching.
Dahlen holds an MSEE from Minnesota State University, Mankato. He has taught in an ABET-accredited electrical engineering program, served as coordinator of an electronic engineering technology program, and instructed military technicians in component-level repair.
Today, he has returned to his home in northern Minnesota, completing a decades-long journey that began with a search for capacitors. Read his story here.