MIPI interfaces & its physical layers characteristics

MIPI (Mobile Industry Processor Interface) is a standard definition of industry specifications designed for mobile devices such as smartphones, tablets, laptops and hybrid devices.The MIPI standard defines three common unique physical (PHY) layers, namely MIPI D-PHY, C-PHY and M-PHY. We can apply each specifications to support a variety of protocol layers and applications.

MIPI D-PHY
MIPI D-PHY is more commonly used in cameras and monitors for smartphones because it is flexible, high speed, low power and a low cost solution. For non-mobile industries, it is also applied for automotive camera sensing systems, anti-collision radars, in-vehicle infotainment systems and dashboard displays. For example, TI’s SNx5DPHY440SS series as per the below figure. The DHY chip automatically compensates for the deviation between the signal source and the data channel of each input pin of the application-level port, so it can reduce circuit redundancy.

MIPI C-PHY
MIPI C-PHY provides high throughput performance through bandwidth-constrained channels, such as connecting the display and camera to the application processor. It provides a PHY for the MIPI Camera Serial Interface (MIPI CSI-2) and MIPI Display Interface (MIPI DSI-2) ecosystems, enabling designers to extend their implementation to support a variety of higher resolution image sensors and displays.

For example, ONSEMI’s FSA660TMX (as below figure) provides a high-speed source switching function.


Firgure 1 Application diagram of FSA660TMX

MIPI M-PHY
MIPI M-PHY is designed for data-intensive applications that require fast communication channels for high resolution images, high video frame rates and large displays or memories. It is a versatile PHY that provides engineers with configuration options and capabilities that can be developed across industry platforms to effectively address multiple markets and use cases.The following is a brief comparison of these three physical layer specifications.

Characteristic M-PHY D-PHY C-PHY
Primary use case Performance driven, bidirectional packet/ network oriented interface Efficient unidirectional, streaming interface, with low speed in-band, reverse channel Efficient unidirectional, streaming interface, with low speed in-band, reverse channel
HS clocking method Embedded Clock DDR Source-Sync Clock Embedded Clock
Channel compensation Equalization Data skew control, relative to clock Encoding to reduce data, toggle rate
|Minimum configuration and pins 1 lane per direction,dual-simplex, 2 pins each (4 total) 1 lane plus clock,simplex, 4 pins 1 lane (trio), simplex, 3 pins
Maximum transmitter swing amplitude SA: 250mV (peak), LA: 500mV (peak) LP: 1300mV (peak),HS: 360mV (peak)
Data rate per lane (HS) HS-G1: 1.25, 1.45 Gb/s, HS-G2: 2.5, 2.9 Gb/s, HS-G3: 5.0, 5.8 Gb/s; (Line rates are 8b10b encoded) 80 Mbps to ~2.5 Gbps (aggregate) 80 Msym/s to 2.5 Gsym/s times 2.28 bits/sym, or max 5.7 Gbps (aggregate)
Data rate per lane (LS) 10kbps – 600 Mbps < 10 Mbps < 10 Mbps
Bandwidth per Port (3 or 4 lanes) ~ 4.0 – 18.6 Gb/s (aggregate BW) Max ~10 Gbps per 4-lane port (aggregate) Max ~ 17.1 Gbps per 3-lane port (aggregate)
Typical pins per Port (3 or 4 lanes) 10 (4 lanes TX, 1 lane RX) 10 (4 lanes, 1 lane clock) 9 (3 lanes)
Version v4.1 (March 2017) v2.1 (March 2017) v1.2 (March 2017)
1 Like

Do you have an idea what’s CSI-2 maximum length mismatch between P/N for the lane ? Seems D-PHY standard directly say about InterLane mismatch only ( < UI/50).

@DigiKey_Internal
Hello
Can anyone help on this request?
Thank you

Interesting question Verna; for MIPI CSI-2 standard, there really is no published restriction that I have seen. However, each supplier will list or define a worst case scenario of an “eye-diagram” as it were, for the receiver limitations;
in other words “what needs to be supplied to the receiver”.

Examples are available for these specifications from Efinix T20 and T120 devices
https://www.efinixinc.com/docs/trion20-ds-v1.0.pdf ; FPGA’s with hardened MIPI CSI-2 interfaces on board. See also Efinix MIPI dev board;

https://www.digikey.com/en/product-highlight/e/efinix/trion-t20-mipi-d-phy-csi-2-development-kit

Also a quick and top level explanation of “Interlace Mismatch“ can be found here on the Xilinx Forum:
image image

I hope this helps

Bill