Interesting question Verna; for MIPI CSI-2 standard, there really is no published restriction that I have seen. However, each supplier will list or define a worst case scenario of an “eye-diagram” as it were, for the receiver limitations;
in other words “what needs to be supplied to the receiver”.
Examples are available for these specifications from Efinix T20 and T120 devices
https://www.efinixinc.com/docs/trion20-ds-v1.0.pdf ; FPGA’s with hardened MIPI CSI-2 interfaces on board. See also Efinix MIPI dev board;
https://www.digikey.com/en/product-highlight/e/efinix/trion-t20-mipi-d-phy-csi-2-development-kit
Also a quick and top level explanation of “Interlace Mismatch“ can be found here on the Xilinx Forum:
I hope this helps
Bill