NAND Gate Logic Works in Simulation but Not on Real Hardware

Hi everyone,
I built a small combinational logic block using NAND gates to generate fault signals before they go into an STM32 interrupt pin. In simulation the truth table is correct, but on hardware I sometimes get false triggers during transitions.

Inputs come from mechanical switches and comparators.

Questions:

  1. Is this likely caused by hazards/glitches in combinational logic?

  2. Would adding latching or Schmitt-trigger inputs be the proper fix?

  3. On the PCB side, should logic IC decoupling capacitors be placed at every chip even for low-frequency signals?

YES … the issue is in the combinational logic … what you’re seeing is classic static/dynamic hazards in combinational logic:

NAND gate paths have slightly different propagation delays
During input transitions, outputs can briefly spike (glitch)
Mechanical switches and comparators make this worse due to slow or noisy edges

So even if the truth table is correct … the timing behavior is not hazard-free in real hardware.

YES … latching or Schmitt triggers will fix it … but there are better options:

Schmitt trigger inputs … cleans slow/noisy transitions (very effective for switches/comparators)
Latch / flip-flop … removes asynchronous glitches completely
Interrupt pin filtering (MCU-side digital filter / debounce) … additional safety layer

In practice:

Schmitt trigger = fixes signal quality
Latch/flip-flop = fixes timing uncertainty
Both together = industrial-grade reliability
REad this discussion, its using both: https://electronics.stackexchange.com/questions/641173/d-type-flip-flop-and-schmitt-trigger

Do decoupling capacitors matter for low-frequency logic ICs? Yes … always … even for low-speed logic:

Switching edges still create high-frequency current spikes
Without local decoupling, supply rails bounce … false switching becomes more likely

0.1 uF ceramic capacitor per IC, placed as close as possible to VCC/GND pins
Optionally one bulk capacitor per board section
You project is small … but I would have suggest to use seperate gnd and power planes … as its the best practise … read these guides on grounding, will help: https://www.aivon.com/blog/pcb-design/the-art-of-grounding-pcb-ground-plane-techniques-for-analog-circuits/
Power and Ground Plane Design Considerations in PCB Layout - PCB Design & Layout - PCBway