(OSD3358) setting mii_sel in the device tree

Embedded Linux Discussions
1

Hi,
u-boot 2019.04
kernel 4.19.106-bone49

I have two Microchip LAN8710 Ethernet PHYs wired as RMII.
My problem is that when the kernel boots, the OSD3358 processor is sourcing the 50Mhz refclk and interfering with the external 50Mhz clock. I think by default the am33xx.dtsi file is setting the gmii_sel register to 0x4 which enables the processor to source the 50Mhz clock. Here is a snippet from the am33xx.dtsi file

phy_sel: cpsw-phy-sel@44e10650 {
	compatible = "ti,am3352-cpsw-phy-sel";
	reg= <0x44e10650 0x4>;
	reg-names = "gmii-sel";
};

I want to set both ports to rmii and set the refclk to input mode by adding an entry in my custom.dtsi file to change the gmii_sel register from 0x4 to 0xC5.

Is the below code the correct way to override the 0x4 with 0xC5 in my custom.dtsi?

&phy_sel {
	reg= <0x44e10650 0xC5>;
}

Thank you,

2

That’s not going to work, the 0x4 is the “size of the cpsw register map”…

Looking at:

https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/devicetree/bindings/net/cpsw-phy-sel.txt?h=v4.19.177

Try, the rmii-clock-ext property:

Optional properties:
-rmii-clock-ext		: If present, the driver will configure the RMII
			  interface to external clock usage

phy_sel: cpsw-phy-sel@44e10650 {
	compatible = "ti,am3352-cpsw-phy-sel";
	reg= <0x44e10650 0x4>;
	reg-names = "gmii-sel";
	rmii-clock-ext;
};

Regards,

3

Robert,
I did not modify the am33xx.dtsi file. I added the following to my custom.dtsi file and the kernel no longer outputs the 50Mhz clock.
…
&phy_sel {
rmii-clock-ext;
};
…

Both PHYs are now getting IP addresses from DHCP and both can ping!
Thank you for your help.