Parity Generator (VHDL)

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parity_generator.vhd (2.0 KB)

Features

  • VHDL source code of a Parity Generator component
  • Configurable number of input bits
  • Configurable selection for even or odd parity

Introduction

Parity evaluates whether the number of “1” bits in a binary code is odd or even. This provides a simple means of error checking. There are two types of parity with opposite results.

Even parity results in a “1” if there are an odd number of “1” bits in the original code, and “0” if there are an even number. The even parity bit can be appended to the code to make the number of “1” bits even.

Odd parity results in a “0” if there are an odd number of “1” bits, and “1” if there are an even number. The odd parity bit can be appended to the code to make the number of “1” bits odd.

This page details a Parity Generator circuit, written in VHDL, for use in FPGAs and CPLDs. The component reads in a binary code over a parallel interface and outputs the parity bit. The size of the input code is configurable, as is whether the output parity bit is even parity or odd parity. It was designed using Quartus Prime, version 17.0.0.

Theory of Operation

This Parity Generator uses simple XOR logic. As the truth table in Figure 1 shows, an XOR gate outputs a ‘0’ if the number of high inputs is even and a ‘1’ if the number of high inputs is odd.

Table 1. XOR Truth Table
truth_table

Figure 1 illustrates the Parity Generator. The parity_eo input makes the correction for even or odd parity, and the cascading XOR gates keep a running evaluation. Each new gate in the series decides if the next bit in the sequence makes the running total odd or even. Once all the input bits are evaluated, the output parity presents the final result.

Figure 1. Parity Generator Circuit

Configuring the Parity Generator

The Parity Generator is configured by setting the GENERIC parameters in the ENTITY. Table 2 describes the parameters.

Table 2. Generic Parameter Descriptions
generic_parameter_descriptions

Port Descriptions

Table 3 describes the Parity Generator’s ports.

Table 3. Port Descriptions

Conclusion

This simple Parity Generator produces the parity bit for a configurable sized binary code. It supports both even and odd parity.

Contact

Comments, feedback, and questions can be sent to eewiki@digikey.com.