The following topics are covered using the Lattice Diamond Design Software version 2.0.1.
• Overview of the Linear Feedback Shift Register
• Using Central Limit Theorem and feedback to shape distribution
• Basic LFSR_Plus.v Core options and configuration
• Sample output distributions (Histograms)
• Writing Pseudo Random Numbers to File using a Test Bench (Verilog Test Fixture)
This Verilog module uses 2 Linear Feedback Shift Registers (LFSR) with polynomials for maximal sequence length, one of which is scalable to output word size (4 to 24 bit) and one to operate as a non-uniform duty cycle clock. The module gives the user 4 options for output distribution types, Gaussian unimodal, bimodal, uniform, and non-uniform distributions. These distributions are created by altering a scalable LFSR output by clocking the output irregularly with a non-uniform clock, shifting scaled outputs into a buffer-adder-tree to effectively use the central limit theorem to create a normal distribution, and a feedback loop to further shape the distributions. Sample histograms are included in the figures following.
The LFSR_Plus.v module is verified in a test bench by writing out the pseudo-random values to a file. This data can be entered into one’s favorite statistical analysis software package for verification. This example uses the Excel statistical add-in package to generate histograms.
The LFSR is a shift register of arbitrary length that takes its input based off a linear function derived from the previous state. This function is chosen to provide a maximally long sequence. As the output-width is scaled, a different LFSR is built with a polynomial to provide maximal length. The polynomials used are commented in the Verilog module.
The Software required/used for this design:
• Lattice Diamond Design Software version 2.0.1 with third party software Synplify Pro for Lattice and Active-HDL Lattice Edition.
The LFSR_Plus.v can be configured by changing the values within the generic parameters within the module’s entity block. The output word width can be scaled from 4 to 24 bits. The type of output distribution can be selected. The size of the LFSR used for clocking can be changed by changing the generic “V” value in the module’s entity. Look to the comments within the module for further guidance.
The design has two output ports, “u_noise_out” and “g_noise_out” for faster validation, two files can be written two at the same time during simulation. The design can be altered to include the complete functionality in one output port with a few Verilog changes within the module.
The RTL diagram for a 4-bit, unimodal and uniform output implementation can be found in Figure 1 below.
Figure 1 – RTL Diagram for LFSR_Plus
The (w-1) bit wide bus shift FIFO is used to implement the central limit theorem and create a Gaussian distribution. Sample “g_noise_out” distribution histograms can be found in figures 2 through 13 below.
Figure 2 – 6-Bit Unimodal Distribution from “g_noise_out” Port
Figure 3 – 6-Bit Bimodal Distribution from “g_noise_out” Port
Figure 4 – 8-Bit Unimodal Distribution from “g_noise_out” Port
Figure 5 – 8-Bit Bimodal Distribution from “g_noise_out” Port
Figure 6 – 10-Bit Unimodal Distribution from “g_noise_out” Port
Figure 7 – 10-Bit Bimodal Distribution from “g_noise_out” Port
Figure 8 – 13-Bit Unimodal Distribution from “g_noise_out” Port
Figure 9 – 13-Bit Bimodal Distribution from “g_noise_out” Port
Figure 10 – 19-Bit Unimodal Distribution from “g_noise_out” Port
Figure 11 – 19-Bit Bimodal Distribution from “g_noise_out” Port
Figure 12 – 21-Bit Unimodal Distribution from “g_noise_out” Port
Figure 13 – 21-Bit Bimodal Distribution from “g_noise_out” Port
Sample “u_noise_out” distribution histograms can be found in figures 14 through 17 below.
Figure 14 – 8-Bit Uniform Distribution from “u_noise_out” Port
Figure 15 – 8-Bit Average-uniform Distribution from “u_noise_out” Port
Figure 16 – 19-Bit Uniform Distribution from “u_noise_out” Port
Figure 17 – 19-Bit Average-Uniform Distribution from “u_noise_out” Port
The included test bench was created from the “generate test bench template” command in the “HDL Diagram” window. Inspect the “LSFR_Plus_tf.v” file by reading the Verilog comments for understanding. Two files are created and opened for writing; the output data for “g_noise_out” and “u_noise_out” are written to these opened files. Simulate long enough to generate enough data to be statistically significant.
Lattice Diamond Design Software version 2.0.1 was used to develop the “LFSR_Plus.v” with supporting software from Synopsis (Synplify Pro for Lattice) and Aldec (Active-HDL Lattice Edition). Diamond can be used as a stand alone development environment with alternative synthesis and simulation software.
This design demonstrates the use of a LFSR based pseudo-random sequence generator using Lattice Diamond Design Software. A test bench highlights the software’s capability to open a file and write output data to it for post-simulation analysis.
Further design support, product tutorials, application notes, users guides and other documentation can be found on the Lattice website