Sampling Audio at 44.1 kHz with the CY8CPROTO-062-4343W Board


The PSoC 6 Wi-Fi BT Prototyping Kit (CY8CPROTO-062-4343W is an inexpensive point of entry to PSoC 6 development. Among its features are two PDM microphones spaced 40 mm apart for stereo audio sampling. These samples are obtained via the PDM-PCM Converter peripheral, which in this tutorial will be configured to collect samples at the standard rate of 44.1 kHz (the same rate used for audio CDs).

ModusToolbox is the development environment of choice for the PSoC 6 family as it includes the PSoC 6 SDK and the ModusToolbox IDE, which itself includes several configurators for the hardware and some middleware. The main configurator, i.e. the Device Configurator, greatly reduces the effort required to configure the device’s system functions and peripherals. Developers can use the graphical interface to set their configuration parameters and the tool will raise a warning/error if any of the arguments are invalid before generating the C code. Of course, this doesn’t mean no work is required on the part of the developer. The Device Configurator is far from perfect and the Architecture Technical Reference Manual (TRM) will most likely have to be referenced for all but the most basic of peripherals. Both of these points are demonstrated in the following tutorial.


Configure the PDM-PCM Peripheral

Let’s begin with the most straightforward step. Table 31-1 in the TRM provides examples of how to configure the timing parameters of the PDM-PCM Converter for several standard sampling rates ( fs).

To enter the values for fs = 44.1 kHz into the Device Configurator, double click on your project’s design.modus file in ModusToolbox IDE. In the ‘Peripherals’ tab, expand the ‘Digital’ resources and select PDM-PCM Converter 0 . In the ‘Parameters’ window, scroll down to the Timing parameters and enter the values as shown below in Figure 1. Note that there is an error in Table 31-1 of the TRM. The Total Divisor Ratio for fs = 44.1 kHz should be 16 rather than 32. This has no impact on the configuration as we do not enter this value directly into the Device Configurator, but it can nonetheless be confusing.

Figure 1: The PDM-PCM Converter’s Timing parameters

The three clock divisors will generate the PDM_CKO clock signal, which is used to clock the external PDM microphones, as follows:

f_{PDM\_CKO}=\frac{f_{CLK−HF[1]}}{(CLK\_CLOCK\_DIV+1)(MCLKQ\_CLOCK\_DIV+1)(CKO\_CLOCK\_DIV+1)}=\frac{45.1584 MHz}{(0+1)(1+1)(7+1)}=\frac{45.1584 MHz}{16}=2.8224 MHz

The SINC_RATE then determines fs according to the formula:

f_s=\frac{f_{PDM\_CKO}}{2∗SINC\_RATE}=\frac{2.8224 MHz}{2∗(32)}=.0441 MHz

While not covered in this tutorial, there are several other parameters to set for the PDM-PCM Converter including channel settings, filter preferences, and interrupt triggers. Please refer to the TRM for more information on these attributes.

Configure the Peripheral Clock

Now comes the complicated part. How do we get an fCLK-HF[1] = 45.1584 MHz? Section 31.2.3 of the TRM presents the External Crystal Oscillator (ECO) in conjunction with a Phase-Locked Loop (PLL) as one solution and I’ve found this works quite well. To modify the configuration for the CLK-HF1 clock, click the chain link icon for the Clock parameter (Figure 2).

Figure 2: Jump to the configuration of the linked clock signal

This will open the ‘Platform’ tab which, among other things, lets you configure the system clocks. In the center of the tab should be an interactive clock diagram which indicates which clocking elements are enabled and how they connect to each other. Following the TRM’s example, we want the internal connections to be made as shown in Figure 3.

Figure 3: Clock diagram with the desired element connections highlighted

We’ll start at the beginning of the path and configure the ECO. If the ECO box is not green, double click it in the clock diagram to enable it. Notice that the ‘Parameters’ window now has several parameters available for us to change. These are the characteristics of the external crystal on the board, which on the CY8CPROTO-062-4343W is a 34.4064 MHz crystal from TXC. Its part number is 8Y34470001 and the TXC 8Y Series Datasheet provides us with all the information needed to configure the ECO peripheral. However, if we try to start by entering 34.4064 into the ‘Frequency (MHz)’ field, we get the following warning:

Unable to evaluate parameter ‘Frequency (MHz)’ on personality ‘ECO’. ‘34.41’ is not within the legal range of [4.00-33.33] for parameter ‘Frequency (MHz)’

This is not a fatal error because the peripheral will still function properly if 33.33 is entered instead of 34.41, but it is rather annoying for reasons we shall soon see. Once this and the rest of the values are entered, the ECO configuration should appear as shown in Figure 4.

Figure 4: The final ECO configuration

Next in the path is the PATH_MUX2 multiplexer. Click on this element in the clock diagram to view its parameters. Choose ‘ECO’ as the Source Clock value (Figure 5).

Figure 5: The final PATH_MUX2 configuration

Next, click the PLL1 element in the clock diagram (double click it if it is not enabled) to populate the ‘Parameters’ window. This is where the consequence of entering an ECO frequency of 33.33 MHz comes back to haunt us. Notice that the Source Frequency is automatically populated with 33.33 MHz. This is what the Device Configurator thinks the PLL reference clock frequency (fref) is. The configurator will perform the following calculation to determine the PLL’s output frequency (displayed in the Actual Frequency field):


By default, the Configuration parameter is set to ‘Automatic’, meaning we can enter our desired output frequency and the Device Configurator will determine the optimal set of divider values that will satisfy the above formula. However, we must keep in mind that it will be performing that calculation with an fref value of 33.33 MHz rather than that the actual fref value of 34.4064 MHz. Therefore, we cannot enter 45.1584 into the Desired Frequency (MHz) field and instead must use an adjusted value calculated as follows:

\frac{34.4064 MHz}{33.33 MHz} = \frac{45.1584 MHz}{f_{out\_adjusted}}

f_{out\_adjusted}=43.745625 MHz

Entering “43.745625” into the Desired Frequency (MHz) field yields the configuration shown in Figure 6.

Figure 6: The final PLL1 configuration.

We can then use the actual value of fref to ensure we will get the correct output with this configuration.

f_{out\_actual}=\frac{f_{ref\_actual}∗FEEDBACK\_DIV}{REFERENCE\_DIV∗OUTPUT\_DIV}=\frac{(34.4064 MHz)∗(84)}{(8)∗(8)}=45.1584 MHz

So while the Actual Frequency field may say 43.745625 MHz, it will actually be 45.1584 MHz as we desired.

Finally, click on the CLK_HF1 element in the clock diagram. Change the Source Clock value to ‘CLK_PATH2’ as shown below in Figure 7.

Figure 7: The final CLK_HF1 configuration

Chose File > Save to save your configuration and generate the source code.