Hello folks on Digiforum,
I’m a newbie here, with a focus on high power Mosfet. Recently I’m looking for way to implement fets with packages allowing top-side cooling, but I’m unsure whether the exposed pad is electrically connected to the junction akin to Infineon’s DirectFet for example.
So I’d like to know whether the exposed pad of these following packages:
- Toshiba’s DSOP Advanced
- Nexperia’s CCPAK1212i
- Onsemi’s TCPAK10, DualCool
- Infineon’s TOLT
is electrically connected to either drain/source tab.
Thanks you for your help!
@minhhung2882001 Upon some further investigation I did find this article regarding the Nexperia package and it’s top plate.
CCPAK1212 package pushes the performance of Nexperia’s power MOSFETs to the next level | Nexperia
The “CC” in CCPAK1212 stands for copper clip, meaning that the power MOSFET silicon die is sandwiched between two pieces of copper, the drain tab on one side and the source clip on the other. With wire bonds entirely eliminated, such an optimized assembly offers a low on-resistance, reduced parasitic inductances, high maximum current ratings and excellent thermal performance.
So, what we interpret that as would be, “finger safe” depends on your circuit in regard to putting a heatsink on the top of the part.
Note that there is no specification for insulation between semiconductor die and the exposed pad therefore we should assume a hard internal connection i.e. the heatsink may not be electrical safe.
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Thanks for your reply!
My intention is to use copper heatsink for high current application, so I want to make sure the exposed pad of these packages are electrically insulated from the junction. However information regarding this important detail is hard to come by. It’s concerning that my hope wasn’t the case though.
How would you suggest designing with these part? I have the idea of using TIM that’s electrically non-conductive, but there’s still the concern that it’ll lose the non-conductive property as time passes and couldn’t guarantee safety.
The datasheets will usually provide an indication, though it may be subtle:
Techniques for designing with such products will vary. A suitable thermal interface qualified for use as an insulation layer is a likely option, both for functional purposes and to avoid turning the heatsink into an antenna that will cause a failure to meet radiated emissions standards. Depending on the application and applicable standards, such a heat sink is often isolated within a device chassis, or connected to a circuit node that will cause a fuse or similar protection device to open in the case of an insulation failure betweent the transistor and heat sink.
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