Value proposition of CFAE HotSpot 3 of 4 – mSIC™ Power Packaging 1st of March 2024 Modules High-Performance Packaging - Slides from Microchip
Benefits of Low Power Loop Inductance
What can one achieve by changing the package to reduce power loop inductance?
62 mm –> SP6LI
15-20 nH –> 3 nH
Lower device cost
Greater system efficiency
To get even more out of SiC, new packaging is required to make systems more efficient, compact and longer-lasting
SP6LI solution is superior to discretes and suitable up to MegaWatt (MW) scale power levels
SiC Design Support – Hardware
PFC = Power Factor Correction
PSFB = Phase Shift Full Bridge
| Part Number | Voltage | Current | RDS(on) Typ. | RDS(on) Max. | SiC parallel diode ratings |
|---|---|---|---|---|---|
| Tc = 80°C | Tj = 25°C | Tj = 25°C | |||
| MSCSM70AM025T6LIAG | 700V | 538A | 2.5 mΩ | 3.2 mΩ | 300A |
| MSCSM120AM02CT6LIAG | 1200V | 754A | 2.1 mΩ | 2.6 mΩ | 300A |
| MSCSM120AM03T6LIAG | 1200V | 641A | 2.5 mΩ | 3.1 mΩ | 250A |
| MSCSM120AM042CT6AG | 1200V | 394A | 4.2 mΩ | 5.2 mΩ | 180A |
| MSCSM170AM029CT6LIAG | 1700V | 530A | 2.9 mΩ | 3.8 mΩ | 300A |
| MSCSM170AM058CT6LIAG | 1700V | 277A | 5.8 mΩ | 7.5 mΩ | 180A |