A Video Introduction and Explanation of the Digital Decade Counter

A decade counter is a digital circuit that counts to 10. This is a modulo-10 operation like our base-10 counting numbers that includes symbol 0 to 9. This video shows the operation of a digital binary counter with the binary results presented in the LED indicators.

Video 1: The 74LS390 decade counter is seen counting in binary from 0 to 9.

Figure 1: Picture of the prototype 74LS390 decade counter driven by a 555 timer.

Where do we find the decade counter?

The 74 series including Integrated Circuits (IC) such as the SN74LS390N pictured in Figure 1 was first released in the mid-1960s and early 1970s. They were very popular components in the decades that followed enabling some of the first personal computers. The decade counter is a natural fit with the seven-segment LED display as the decimal digits (symbols 0 to 9) could be used to drive the segmented LED display via a LED driver IC.

Select member of the 74-logic series are still found in today’s electronics. However, their digital dominance has decreased significantly. Small, yet powerful, microcontrollers have largely replaced the older technology. In truth, presenting a 74LS390 decade counter such as the one pictured in Figure 1 has become an academic exercise. You are unlikely to encounter such a physical device in new equipment.

Today, the most likely place to encounter a decade counter is inside a Field Programmable Gate Array (FPGA). The counter will likely be described using a hardware description language such as Verilog or VHDL. The second most likely place is an academic setting.

Why do we need to understand the decade counter?

One of life’s inconvenient facts is the difference between experts and learners. While I can state that the physical decade counter embodied in the 74-logic series is an antique, in no way does this diminish its importance. As a future technician or engineer you need to understand the concept. This includes the concept of a divide by 2 and the divide by 5 circuitry internal to the 74LS390. It also includes the physical skill associated with building a functional circuit.

The expert / learner dichotomy is readily apparent in the FPGA. While the expert is unlikely to use the 74 series logic, careful study of the 74 series logic serves as a good way to learn how to program. The old ways of dividing a circuit into smaller pieces is still relevant for a clean hierarchical design. Study of the functions encapsulated into the old design suggests ways to divide and conquer new designs. The decade counter is one such building block.

Tech Tip: Circuit decoupling is an important but often overlooked design aspect. It is important to include power supply bypass capacitors such as shown in the lower left-hand side of Figure 2. These capacitors prevent disturbances (switching events) from entering or exiting an IC. This is vital in a counting circuit as any power supply rail disturbances can trigger the counting circuit causing an erratic count. Additional information about breadboard stability may be found in this TechForum article.

How does the decade counter work?

Let’s first consider the operation of a wall clock. The second hand performs a modulo-60 operation. Ignoring fraction seconds, the second hand can take on 60 unique values from 0 to 59. At second 59, it does not proceed to second 60, instead it resets to second 0.

The decade counter performs the same operation except with a modulo-10 operation. It can take on values from 0 to 9. As count 9 it does not move to 10, it resets to 0.

Tech Tip: There is a long-standing bug associated with the way we think about counting. It’s called an Off By One (OB1) error with an intentional reference to our space-traveling mentor. It is easy to make a mistake by describing a module 10 system but then stating that we begin counting at 0. The most common OB1 error is to begin counting at 1 when we should have started at 0. This is particularly true with computer programming where we incorrectly index items in an array.

Detect and reset functions can be performed in two ways. We could design a circuit to monitor a binary count looking for the number 10. Upon detection, the circuit would reset the counter back to zero. We could also recognize that 10 = 2 x 5. This suggests that the problem may be split into 2. The first part of the circuit is a single flip-flop divider to perform the divide by 2 operations. The remainder of the circuit is a divide by 5. Here circuitry is looking for the number 5 before performing the reset. This second method is physically implemented in the 74LS390 IC.

Figure 2 shows the 2 * 5 counter operation. Before we start, observe that the schematic is divided into 3 sections. On the left we see a 555-timer circuit. This is a simple astable oscillator to provide a pulse approximately once a second. Click here for an online calculator to determine the 555 operating parameters and to assist with component selection. On the right are two identical sections of the 74LS390 labeled as U2A (upper) and U2B (lower)

Looking closer at U2A we see three sections:

  • top: reset
  • middle: divide by 2
  • bottom: divide by 5

In this example, the output of the divide by 2 circuit (pin 3) is used to drive the divide by 5 (pin 4). The result is the desired divide by 10 operation originally shown in Video 1.

Figure 2: Schematic drawing of a 74LS390 decade counter with a 555-timer driver.

What topics are related to the decade counter?

There is an entire family of counters and counter like functions. As a continuation of the 74-series logic look for counters with different bit-widths as well as counters that can count up as well as down. As a challenge consider the steps necessary to build a 100 second stopwatch or a 100 second kitchen timer. Do try to build the device in the style of Ben Eater. Alternatively, you could explore the operation using simulation tools such as CircuitVerse. A Verilog or VHDL FPGA solution is certainly a steppingstone in your future.


As an educator I’m content to direct you to build a decade counter such as the one presented in the opening video. You will learn valuable lessons in construction, troubleshooting, and the importance of bypass capacitors to prevent an erratic count. Going forward, I encourage you to apply these lessons to FPGA based designs using Verilog and VHDL. Let the older circuit and their natural -informed - divisions guide your future designs.

About the Author

Aaron Dahlen, LCDR USCG (Ret.), serves as an application engineer at DigiKey. He has a unique electronics and automation foundation built over a 27-year military career as a technician and engineer which was further enhanced by 12 years of teaching (interwoven). With an MSEE degree from Minnesota State University, Mankato, Dahlen has taught in an ABET accredited EE program, served as the program coordinator for an EET program, and taught component-level repair to military electronics technicians. Dahlen has returned to his Northern Minnesota home and thoroughly enjoys researching and writing articles such as this. LinkedIn | Aaron Dahlen - Application Engineer - DigiKey