Be Aware of Latch Up Problems


#1

“Latch Up” is a condition wherein a low impedance path is generated between a device’s supply pin and ground. This condition will be caused by a trigger event (current injection or overvoltage), but once triggered the low impedance path remains even after the trigger condition is no longer present. This low impedance path may cause system turbulence or catastrophic damage due to excessive current levels. In the circuit design phase for your application, please ensure that the voltage and current levels applied to devices always adhere to the absolute maximum ratings.

The following suggestions will help you prevent latch up problems.

  1. Ensure that diodes are connected in series with VDD if latch up is occurring due to power-up sequencing
    If the digital inputs or outputs of a device can go beyond VDD at any time, a diode (such as a 1N914) connected in series with VDD will prevent SCR action and subsequent latch-up. This works because the diode prevents the base current of the parasitic lateral-PNP transistor from flowing out the VDD pin, thus preventing SCR triggering.
    Fig%201

  2. Adding Schottky diodes to DGND (digital ground) protects against undervoltage events.
    If the digital inputs and outputs of a device can go below DGND at any time, a Schottky diode connected from those inputs or outputs to DGND will effectively clamp negative excursions at –0.3 volts to –0.4 volts. This prevents the emitter-base junction of the parasitic NPN transistor from being turned on, and also prevents SCR triggering.
    Fig%202

  3. Connecting Schottky diodes between DGND and AGND
    If the DGND potential can occasionally exceed AGND by more than 0.3 volts, a Schottky diode placed between the two pins of the device will prevent conduction of the associated parasitic NPN transistor. This provides additional protection against latch-up. Also, An extra diode connected in inverse parallel with the one just mentioned provides clamping of DGND to AGND in the other direction and will help to minimize digital noise from being injected into the device.
    Fig%203