Please refer to out previous article Part 2 of the additional setup for the DE-25 Agilex 5 Simics Simulator before preceeding with the next steps. The goal of this article is to build a Zephyr RTOS application that will run in the Agilex™ 5 Simics Virtual Platform relevant to the DE-25 FPGA Dev Kit
As in our previous ARM Trusted article in Part 1 proceed with the following,
git clone -b QPDS24.3_REL_GSRD_PR https://github.com/altera-opensource/arm-trusted-firmware arm-trusted-firmware-sdcard
cd arm-trusted-firmware-sdcard
git switch -c test
make realclean
ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu- make PLAT=agilex5 SOCFPGA_BOOT_SOURCE_SDMMC=1 bl2 bl31 PRELOADED_BL33_BASE=0x80100000 -j$(nproc)
make fiptool
cp tools/fiptool/fiptool $TOP_FOLDER
Build the Zephyr application for the Zephyr RTOS DigiKey drinking coffee cup philosophers,
cd $TOP_FOLDER
source venv/bin/activate
cd $TOP_FOLDER/zephyrproject/zephyr
west build -b intel_socfpga_agilex5_socdk samples/philosophers -d agilex5 --pristine
deactivate
To run this Zephyr application in the Simics Agilex 5 simulator,
cd $TOP_FOLDER
mkdir qspi_bin && cd qspi_bin
cp $TOP_FOLDER/arm-trusted-firmware-qspi/build/agilex5/release/bl2.bin .
$TOP_FOLDER/fiptool create --soc-fw $TOP_FOLDER/arm-trusted-firmware-qspi/build/agilex5/release/bl31.bin --nt-fw $TOP_FOLDER/zephyrproject/zephyr/agilex5/zephyr/zephyr.bin fip.bin
Create the corresponding .pgf file,
#CREATE PFG FILE
cd $TOP_FOLDER/qspi_bin
tee qspi_flash_image_agilex5_boot.pfg << 'EOF'
<pfg version="1">
<settings custom_db_dir="./" mode="ASX4"/>
<output_files>
<output_file name="flash_image" directory="." type="JIC">
<file_options/>
<secondary_file type="MAP" name="flash_image_jic">
<file_options/>
</secondary_file>
<secondary_file type="SEC_RPD" name="flash_image_jic">
<file_options bitswap="1"/>
</secondary_file>
<flash_device_id>Flash_Device_1</flash_device_id>
</output_file>
</output_files>
<bitstreams>
<bitstream id="Bitstream_1">
<path hps_path="bl2.hex">agilex5_factory.sof</path>
</bitstream>
</bitstreams>
<raw_files>
<raw_file bitswap="1" type="RBF" id="Raw_File_1">bin/fip.bin</raw_file>
</raw_files>
<flash_devices>
<flash_device type="MT25QU02G" id="Flash_Device_1">
<partition reserved="1" fixed_s_addr="1" s_addr="0x00000000" e_addr="0x001FFFFF" fixed_e_addr="1" id="BOOT_INFO" size="0"/>
<partition reserved="0" fixed_s_addr="0" s_addr="auto" e_addr="auto" fixed_e_addr="0" id="P1" size="0"/>
<partition reserved="0" fixed_s_addr="0" s_addr="0x03C00000" e_addr="auto" fixed_e_addr="0" id="fip" size="0"/>
</flash_device>
<flash_loader>A5ED065BB32AE6SR0</flash_loader>
</flash_devices>
<assignments>
<assignment page="0" partition_id="P1">
<bitstream_id>Bitstream_1</bitstream_id>
</assignment>
<assignment page="0" partition_id="fip">
<raw_file_id>Raw_File_1</raw_file_id>
</assignment>
</assignments>
</pfg>
EOF
and finally,
cd $TOP_FOLDER/qspi_bin
aarch64-none-linux-gnu-objcopy -v -I binary -O ihex --change-addresses 0x00000000 bl2.bin bl2.hex
cd $TOP_FOLDER/qspi_bin
ln -s $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0_hps.sof agilex5_factory.sof
quartus_pfg -c qspi_flash_image_agilex5_boot.pfg
Now we are ready for the final steps to run the Zephyr RTOS DigiKey drinking coffee cup philosophers in our next article. The DE-25 FPGA Dev Kit is a powerful platform featuring an HPS/FPGA Agilex 5 (available as D-Series and E-Series depending on the case) capable of implementing Tensor AI slices,
that go beyond what traditional/classical old school DSP slices implemented in the past,
and it is available at DigiKey.
Have a wonderful day
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