DPOT AD5160 Pmod Controller (top-level file): pmod_dpot_ad5160.vhd (7.4 KB)
SPI Master (must also be included in project): spi_master.vhd (8.8 KB)
- VHDL source code of a streamlined interface to Digilent’s Pmod DPOT (Pmod for Analog Devices AD5160 digital potentiometer)
- Accepts data to set the digital pot using a simple parallel interface
- Handles all serial communication with the DPOT Pmod
- Configurable system clock rate
This details a VHDL component that handles interfacing to the Digilent’s DPOT AD5160 Pmod, shown in Figure 1. Figure 2 illustrates a typical example of this Digital Pot Pmod Controller integrated into a system. As shown, the DPOT Pmod Controller connects to the Pmod ports and executes transactions to set the digital pot’s resistance. Data is latched in on a simple parallel interface which can be connected to user logic or to input ports on the FPGA.
Figure 1. Digilent DPOT Pmod
Figure 2. Example Implementation
The DPOT Pmod provides a 10kΩ digital potentiometer with 8 bits of resolution, from the AD5160 family. The resistances RWB and RWA are set using an SPI interface. The minimum resistance is determined by the wiper contact resistance RW , typically 60Ω. (However, in my sample it measured 89Ω.) The pot has 256 contacts points that the wiper can access between the A and B end points, so the resistance is set in increments of ~39Ω per bit. Equations 1 and 2 define the resistances RWA and RWB , respectively.
The DPOT Pmod Controller uses a simple state machine and the SPI Master component available on eewiki to set the digital pot’s wiper location.
The design uses the state machine depicted in Figure 3 to implement its operation. Upon start-up the component immediately enters the start state. It remains in this state for 100us to ensure the Pmod has ample time to power-up. It then proceeds to the pause state. Here, it ensures at least 100ns elapse between transactions with DPOT (the AD5160 datasheet specifies a minimum of 40ns). It then deasserts the busy signal to indicate that the DPOT Pmod Controller is ready for a new transaction with the DPOT Pmod and proceeds to the ready state. It waits in the ready state until the dpot_tx_ena enable signal is asserted, when it latches in the data for the new transaction and advances to the send_data state. In this state, it executes the transaction with the Pmod and then returns to the pause state. Although not shown, resetting the component at any time returns it to the start state.
Figure 3. State Diagram
During the send_data state, the state machine controls an SPI Master component to communicate with the digital pot on the Pmod. Documentation for the SPI Master is available here.
The SPI Master is configured with CPOL = 0 and CPHA = 0, to meet the requirements of the AD5160 digital potentiometer.
The clocking of this DPOT Pmod Controller is configured by assigning values to the GENERIC parameters clk_freq and spi_clk_div, defined in the ENTITY. The clk_freq parameter must be assigned the frequency of the system clock provided on the clk input port in MHz. Equation 3 defines how the spi_clk_div value is calculated.
where fclk is the frequency of the provided system clock in MHz.
For example, the default value specified in the code is spi_clk_div = 1. This is arrived at because the component was developed and tested using a system clock of 50 MHz. 50/50 = 1. Any clk_freq ≤ 50 MHz results in the default spi_clk_div = 1.
Equation 4 defines the serial clock frequency fsclk that results.
This calculation keeps the serial clock below the digital pot’s maximum specified communication frequency of 25 MHz.
The DPOT Pmod Controller indicates its availability on its busy output. When the busy signal is ‘0’, the Controller is ready to accept transactions to send to the DPOT Pmod. Asserting the dpot_tx_ena input latches in the current value of dpot_data. Once latched, the Controller asserts the busy signal to indicate that a transaction is in progress, so it is not currently available. When the transaction is complete, it again deasserts the busy signal to indicate that it’s ready to accept another request.
Figure 4 illustrates an example transaction. The busy signal is ‘0’. The user logic then asserts the dpot_tx_ena signal to send the data presented on the dpot_data bus to the DAC. The Controller asserts the busy signal, indicating the request is latched in, at which point the user logic can deassert the dpot_tx_ena signal. The Controller sends the serial communication to the DPOT Pmod, then deasserts busy once the transaction and the 100ns pause is complete.
If the dpot_tx_ena signal is not deasserted, a new transaction request is latched in and begins immediately once the Controller is available.
Figure 4. Transaction Example
Table 1 describes the DPOT Pmod Controller’s ports.
Table 1. Port Descriptions
This Pmod has a 6-pin connector, J1. Table 2 provides the pinout for this connector. The DPOT Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.
Table 2. DPOT Pmod Pinout and Connections to DPOT Pmod Controller
The reset_n input port must have a logic high for the DPOT Pmod Controller component to operate. A low logic level on this port asynchronously resets the component. During reset, the component aborts the current transaction with the DPOT Pmod and sets the busy output high to indicate it is not available. Once released from reset, the DPOT Pmod Controller restarts operation.
This DPOT Pmod Controller is a programmable logic component that interfaces to Digilent’s DPOT AD5160 Pmod. It simplifies data transactions with the digital pot to set its resistance.
Comments, feedback, and questions can be sent to firstname.lastname@example.org.