How to Implement a PNT derived Pulse Per Second (PPS) External Trigger for an ADC and FPGA

This engineering brief is focused on techniques applicable to Precision Timing and Navigation (PNT) equipment. Specifically, it addresses the problem of triggering a data collection system using a Pulse Per Second (PPS) signal. We assume that the data collection equipment consists of a high-end Analog to Digital Converter (ADC) demo board attached to a matching high performance Field Programmable Gate Array (FPGA).

Comparing the ADC / FPGA combination to an oscilloscope

An ADC is not an oscilloscope, yet it can perform oscilloscope like functions with the proper software. This is especially true if a high-performance ADC is coupled to an FPGA.

Recall that most oscilloscopes have a trigger input. We can adjust the trigger threshold in many ways. For example, we could trigger on the rising edge of a 3.3 VDC pulse PPS when it crosses a 1.65 VDC threshold. From the user perspective, we can fine tune this threshold voltage up or down bounded only by the amplitude of the trigger waveform. If the signal has a slow rise time, moving the trigger threshold moves the displayed waveform slightly to the right or to the left. In this way, we maintain the signal start at the intersection of oscilloscope time zero (no delay assumed) and trigger threshold voltage.

At least, that describes the user experiences for an analog oscilloscope.


Let me shift gears with a related story. Have you ever driven an electric car? My first experience was back in the 1990s with the EV1. I was surprised that the car would creep forward at the intersection; take your foot off the brake and the car would go about 5 MPH. The engineers had captured the feel of an internal combustion engine car with an automatic transmission.

The electric car experience mirrors the experience we have when shifting from the old analog to the new digital oscilloscopes.


What is a digital oscilloscope?

A digital oscilloscope is a fancy shell for several high-performance ADCs. This includes the primary dual or quad channels along with the trigger input. The waveform we see on the screen is not a true representation of the data as captured and then held in the oscilloscope’s high-speed memory. Instead, it’s a smoothed connect-the-dots version of the finite sampled data. It’s like that EV1 where the oscilloscope engineers kept the look and feel of the old system.

This statement applies to the oscilloscope’s trigger as well. While we experience a smooth continuous motion when we adjust the trigger level, it is anything but. Instead, there is a certain behind the scenes code artistry with interpolation between the points.

Tech Tip: Some oscilloscopes have the option to showing or otherwise marking the location of the sampled data within the smooth curves. This is a useful reminder of finite nature of the data captured by the digital oscilloscope. It shows the discrete samples sliced in both time and amplitude.

What is a Pulse Per Second signal?

Before exploring how to trigger the ADC, let’s explore one of the mainstays of the PNT world. Specifically, let’s examine the atomic clock such as the IQD ICPT-1 Rubidium Oscillator. The Rubidium oscillator is representative of a wide range of PNT clocks, oscillators, and related systems such as the Global Positioning System (GPS).

These modern Rubidium and Cesium atomic clocks are a miracle of technology. For comparison, consider an inexpensive wall clock. It may lose a few seconds over the course of a month. That same clock mechanism driven by properly disciplined Rubidium oscillator may lose a fraction of a second over a human lifetime.

The Pulse Per Second is a high-performance output signal associated with PNT equipment. It’s common to use the PPS along with other signals such as 10 MHz to discipline other PNT clocks. A perfect example is your GPS receiver or GPS breakout board where the clock, and consequently, the PPS in your GPS receiver is “set” by the atomic clocks flying in the GPS satellites. These GPS satellite clocks are constantly monitored Space Delta 8 at Schriever Air Force Base in Colorado. The GPS clocks are “set” by an ensemble of clocks maintained by laboratories across the world. It’s important to realize that your GPS signal can be linked back to the world’s time clocks that define Coordinated Universal Time (UTC). This includes the clocks at locations such as NIST and USNO. An example 5071A cesium beam tube oscillator from NIST is shown in Figure 1. This is an older picture taken from the Author’s visit to the NIST facility in Boulder Colorado.

Figure 1: Thermal chamber home for a 5071A cesium beam tube oscillator operating as part of the NIST clock ensemble.

The Pulse Per Second (PPS) is considered a standard output signal for PNT devices. This includes the previously mentioned Rubidium atomic clock as well as most, but not, all GPS receivers. Many devices also include 1 MHz, 5 MHz, a 10 MHz reference signal(s) from which the PPS signal is derived. The PPS is typically digitally generated and linked to the high frequency oscillator signal. This is an important signal later in our discussion.

From this point forward, we will collectively refer to the 1 MHz, 5 MHz, or the 10 MHz signals as simply 10 MHz. Also, for convenience, we will use the term Rubidium when referring to a PNT device with both a PPS and 10 MHz outputs. A picture of a modern Rubidium oscillator is included as Figure 2.

Figure 2: Picture of the IQD ICPT-1 Rubidium Oscillator from the datasheet.

Attributes of the PPS signal

The PPS signal is a square wave. We can handle it just like any other digital logic signal. For a 3.3 VDC device we can expect a 3.3 VDC logic pulse relative to ground. Some devices may be programmed for a variable pulse width.

The rising edge of the PPS signal will be synchronized with the 10 MHz internal oscillator of the associated device. As previously stated, the PPS is digitally derived by a divider circuit driven by the clocks high-frequency clock. As a rule, the PPS signals are synchronized to within +/- 50 ns or better for high end devices.

History: The terms Precision Time and Navigation (PNT) may not appear related. However, the relationship couldn’t be more important as precision time has been an essential component of navigation since the late 1700 with the development of Harrison’s Chronometer. Please see Video 1 for a visualization of time relating to distance from one of the great pioneers of computer programming.

Video 1: An interview with retired Admiral Grace Hopper (pioneer of computer programming). See time index 4:20 for a visualization of the nanosecond.

How to trigger an ADC in a PNT setting

The ADC and FPGA are digital devices. The timing for these systems is based on the clock that feeds the FPGA. This may or may not include a Phase Lock Loop (PLL) to increase the clock speed. This PLL allows a high-speed clock to be developed inside the semiconductor die without resorting to high frequency external wires on the PCB with all their inherent problems.

It’s safe to say that clock performance is tied directly to cost. While the default oscillators (clocks) associated with the ADC or FPGA are good, they are generally not in the PNT family. For instance, the Rubidium oscillator by itself costs more than most FPGA demo boards.

But that’s the point, and the very reason you are reading this article. You are looking for a way to synchronize your ADC / FPGA system to a PPS signal.

Pass the PPS directly to the FPGA fabric

It is possible for the FPGA to directly read the PPS signal. After all, the PPS is, or could be level shifted to a 3.3 VDC logic signal. This may be good enough for many applications. However, there is a problem.

As an analogy, suppose we had two digital wall clocks representing the GPS generated PPS and the FPGA. Let one clock run slightly faster than the other. As we start this thought experiment, let the clocks agree with each other. Sometime later, we need to reset clock #2 to match clock #1. This isn’t too difficult if we are allowed to halt time in clock #2. For example, set clock #2 to minute 15 and press the halt button. As soon as clock #1 toggles to minute 15 (a rising edge event), we let go of the halt button on clock #2. In theory, both clocks are set to the same time.

The problem in this thought experiment is the sampled nature of our FPGA based clock #2. The clause “as soon as clock #1 toggles” is complicated by the ticking (sampling nature) of clock #2. Assuming clock #2 is a sampled system with appropriate clock boundary protection, the clause becomes “as soon as clock #1 and on the next rising edge of clock #2.”

Another way of saying this is that there will always be an uncertainty of the FPGA’s interpretation of the PPS time zero. With a FPGA running at 100 MHz, the uncertainty is bounded at the 10 ns period. In a sampled system the PPS trigger will experience 10 ns jumps as the clocks slide in time relative to each other. There are also smaller problems that arise due to the uncertainty of the logic threshold voltage. The exact voltage level differentiating a logic 0 from a logic 1 may vary from device to device and with temperature. However, the effect is small especially when we consider the calibration for things like the length of PPS cable (approximately 1 ns per foot delay).

Use the Rubidium high-frequency signal as the ADC sample clock

Direct use of the 10 MHz signal from the Rubidium source is viable for some applications. For example, we could drive the ADC sample clock with a 10 MHz signal. By Nyquist, we configure the ADC’s front end low pass filter to remove all signals above 5 MHz. Inside the FPGA, we can then use a clock synchronizer to cross the 10 MHz samples into the higher speed FPGA clock domain.

The problem with this technique is the previously mentioned PPS clock uncertainty. While the ADC will run true, we will not be able to resolve the PPS timing to anything less than the clock period of the FPGA.

Use a free-running ADC clock, sample the Rubidium’s high frequency oscillator, and use a PPS trigger.

Recall that the PPS is derived from a digital counter driven by the Rubidium’s high frequency oscillator. It stands to reason that there is a fixed Time Of Coincidence (TOC) relationship between the rising edge of the PPS and the 10 MHz clock signal. We could use this fixed TOC relationship to synchronize the Rubidium and FPGA.

Consider how this looks on an oscilloscope. Let the scope trigger on the PPS. The 10 MHz signal would appear stationary (TOC event) with very little jitter between consecutive seconds. By way of analogy, think of this a wall clock with the PPS signal as the minute hand and the 10 MHz as the second hand. Except this time, the fine time measurement can dip into the low nanosecond or even the picosecond range.

We now let the PPS trigger the FPGA. We also sample the 10 MHz signal using one of the ADC channels. Using the course / fine analogy, the FPGA is now aware of the PPS. It serves as a “get ready” signal as the FPGA will base the actual fine-time measurement on the next positive zero crossing of the 10 MHz signal.

Surprisingly, we can change the TOC relationship by changing the relative length of the PPS and 10 MHz connecting cables (approximately 1ns per foot). With this technique we can place the 10 MHz TOC a comfortable time distance behind the PPS. By the way, don’t let future technicians clean up the equipment racks by shortening the cables.

Without correction, our timing is still at the mercy of the FPGA / ADC free-running clocks.

One way to eliminate this problem is to interpolate the samples of the 10 MHz signal. This technique is suggested in Figure 3. First, we select the sample immediately above and immediately below the zero crossing. We then perform a calculation using similar triangles to identify (interpolate) the timing of the zero crossing. With this method we can obtain an estimate with much greater resolution than the course PPS trigger. A measurement that must be calibrated to include the length of the connecting cables.

There were many steps to the process. Let’s restate the algorithm:

  1. Wait for a PPS signal to establish the course time reference point.

  2. Capture the datapoints associated with the next 10 MHz zero crossing including one data point below and one immediately above the zero crossing. This will form the bases of the fine-time reference point.

  3. Calculate time zero as a fraction of sample time using the algebra associated with similar triangles.

  4. If necessary, refine the technique by calculating the exact frequency of the ADC sample clock. This can be done by implementing a frequency counter counting the number of ADC clock (samples) completed in one second.

  5. Use multiple ADCs, all with a common sample clock, to determine timing for multiple oscilloscope-like channels. Data could be stored in a FPGA buffer that begins to fill at the fine PPS TOC. A ring buffer could also be used with an index that is captured at the TOC.

  6. Anchor (effectively time stamp) all samples using the refined reckoning of the ADC sample frequency. Stated another way, we can establish the passage of time by counting the number of samples that have occurred and then add the fractional piece calculated using the similar triangles.

  7. Adjust as necessary to limit the complexity and cost of this highly complex and energy-intensive application. Sample just fast enough to get the job done (Nyquist) and store just enough data. Shut down the sampler when possible. We could even consider a hardware solution to lower cost and save energy. If the project’s timing requirement allow hardware such as solid-state switches or even relays could be used to minimize the total number of required ADCs. In short, optimize where possible.

Figure 3: Interpolating to find the exact time of the positive zero crossing.

Steer a FPGA driven Direct Digital Synthesizer (DDS)

Before departing we should mention that the FPGA and advanced microcontrollers can implement Direct Digital Synthesis (DDS) with high bit rates. With the proper control algorithm (steering) the FPGA can maintain an internal reckoning of time that is phased locked to an external source.

Back to our dual wall clock synchronization analogy, clock number 2 can self-correct so that it tracks clock #1. Instead of a periodic time adjustment, we can implement continuous adjustments. This is advantageous as clock #2 now has some limited ability to determine when things go wrong with clock #1.

What is Direct Digital Synthesis?

The DDS is a digital technique used to develop a sine wave. It is typically implemented as a modulo-N adder (phase accumulator) and large Look Up Table (LUT) containing N-bit values representing a sampled sinusoid. A Digital to Analog Converter (DAC) may then be used to produce a physical sinusoid signal derived from the DDS. A high-performance FPGA based DDS may have a 32-bit phase accumulator and a 16-bit LUT. The wide accumulator facilitates fine frequency adjustments while the 16-bit (signed) LUT provides a high-fidelity reproduction of the sinusoid or arbitrary signal if desired.

The DDS is driven by a high-speed oscillator preferably with a frequency at least ten times the signal to be reproduced. For every rising edge of this oscillator, the DDS phase accumulator will add the user desired Phase Increment Number (PIN) to itself. The resulting number is used to index the desired number from the LUT.

Tech Tip: To save memory the DDS LUT may only contain the first quadrant data describing a sinusoid. A simple FPGA based routine determines the appropriate sinusoid quadrant based on the number held in the phase accumulator. The index into the LUT is adjusted as necessary. Also, the LUT values are negated as necessary to develop the full 4-quadrant sinusoid representation.

To fully understand the DDS we need to review our trigonometry and use some wall clock math. For starters, let’s define a sinusoid in terms of the wall clock’s second hand. At second zero the sinusoid has zero amplitude, 90 degrees (15 seconds) later the amplitude is 1, at 180 degrees (30 seconds) the amplitude is 0, and at 270 degrees (45 seconds) the amplitude is -1. The point of this analogy is to recognize that the sinusoid is a function of the position if the clock’s second hand.

Consider what happens when we change the gears associated with the second hand. Our concept of the second is the same as the clock still ticks every second. This tick represents the oscillator driving the DDS. If the gears slow down the second hand by a factor of two, we now have a DDS that produce a 2 Hz signal. Likewise, if the gears are sped up by a factor 5, the clock produces a sinusoid with a 200 ms period.

In this wall clock analogy, the gears are like the phase accumulator and PIN. The position of the second hand is like the LUT. Changing the PIN changes the frequency of the sinusoid. The higher the PIN, the higher the DDS frequency.

Stability of the DDS

The DDS is only as stable as its driving oscillator. To give you an idea of the sensitivity, consider Figure 4. This is a picture of FPGA / ADC installed in a box to improve thermal stability. When operating, this box was closed and wrapped in a blanket. Notice that many water bottles are included in the box to increase the system’s thermal mass thereby slowing down the rate of clock change. In hindsight an Oven Controlled Crystal Oscillator (OCXO) would have been a nice addition to the project.

These extreme measures may be required when dealing with measurements in the nanosecond range. As I recall a slow breath, or a touch of the finger would cause the stock FPGA oscillator to shift when viewed at the nanosecond level relative to another clock. Normally, we never notice such things but that is not the case when we enter the land of PNT. Also, with regards to thermal stability, notice that the Cesium 5071A oscillator in Figure 1 is also installed in a thermal chamber.

Figure 4: Author’s FPGA based DDS and sampler enclosed in a box with multiple water bottles to increase thermal mass.

Parting thoughts

This is a long article to answer what appears to be a simple question. In some cases, a direct connection of the PPS to a microcontroller of FPGA is all that is required. It’s an easy low-cost solution that will yield good results. However, as we approach the nanosecond and then reach into the picosecond measurements the cost and complexity quickly rise.

There is certainly more to this complex topic. Yet, I hope this introduction to PNT focused though the lens of the FPGA sheds light on the beating heart of our critical nation timing infrastructure.

Best Wishes,

APDahlen

About the author

Aaron Dahlen, LCDR USCG (Ret.), serves as an application engineer at DigiKey. He has a unique electronics and automation foundation built over a 27-year military career as a technician and engineer which was further enhanced by 12 years of teaching (interwoven). With an MSEE degree from Minnesota State University, Mankato, Dahlen has taught in an ABET accredited EE program, served as the program coordinator for an EET program, and taught component-level repair to military electronics technicians. Dahlen has returned to his Northern Minnesota home and thoroughly enjoys researching and writing articles such as this. LinkedIn | Aaron Dahlen - Application Engineer - DigiKey

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