I wanted help regarding merging and verifying IP cores

I am trying to merge and verify an xADC IP core with FFT IP core and observe the results.

Furthermore, I would need to change the memory address of xADC to FFT to acces the processed data in Xilinx SDK?
I am not sure how to proceed on this and needed help on this.

Hi Pratyush ,

Thanks for your inquiry. @RobertCNelson @David_1528 @Matt_Mielke @APDahlen any ideas on this one?

Sorry, @Pratyush,

Recommend you consult Xilinx or post the question on Vivado forums. You’ll find a supportive community of experienced FPGA programmer on forums such as Vivado (amd.com).

Best Wishes,

APDahlen