## Features

Infinite Impulse Response Filters can be used in many applications, from audio to data processing, with low processor overhead. One bi-quad section can consume as little as 5 (18-bit) multipliers in an FPGA, up to 20 if 32-bit word lengths are required. The following design topics will be covered:

• IIR filter bi-quad section design fundamentals

• Filter stability and the Z transfer function

• Excel based Bi-linear Z transform IIR design tool

• Filter scaling for more efficient implementation

• Filter Characteristics and Validation

• Custom VHDL component design and instantiation to include an 18-bit CODEC controller and both 18 and 36-bit IIR bi-quad sections

## Introduction

This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) LM4550 audio CODEC. The design was developed in Xilinx ISE ver13.1. This design employs an audio CODEC, but sensor data can also be filtered, hence the CODEC is not required. The IIR filter also works well to filter sensor data. The filter can be scaled down to smaller word lengths, in this way it can be used as a starting point to redesign a custom IIR filter for faster implementation. The Xilinx Spartan 6 FPGA is a good choice for DSP logic circuit design due to the integrated DSP48A1 blocks. The integrated DSP blocks allow for parallel math circuits resulting in a filter capable of ultra fast data processing. The IIR utilizes 32x32 and 32x18 bit multipliers, as well as several adders in both the feed-forward and feedback paths. The IIR filter can be used with any FPGA given enough hardware multipliers, taking into account the word length of the filter.

## Background

It is not necessary that the user of this module have complete understanding of IIR filter design, but it can help in trouble shooting a filter if one understands the basic design principles. This background section covers the fundamentals of the IIR filter design to include the bi-linear z-transformation and VHDL module design itself. The IIR filter is a recursive filter designed from an analog transfer function prototype. The bilinear z-transformation is a linear approximation which maps the s-Domain transfer function to the discrete z-domain. In doing this the jw(j-omega) axis is mapped to the unit circle via frequency warping as a result of the Nyquist sampling rate, Fs/2. The warping relationship is seen in equation 1 below. The s-domain (equation 2) then can be transformed into the z-domain where “z^-1” is the delay operator. The bi-quadratic is simply two delay lines; one is a feed-forward path and the other a feedback path. The z-transfer function is seen in equation 3 below. The bi-quadratic block diagram can be seen in figure 1 below.

**Equation 1**

**Equation 2**

**Equation 3**

**Figure 1 – Bi_Quadratic Signal Flow Block Diagram**

The feed back path can cause filter instability. In the s-domain the filter is considered stable if the poles lie in the left half plane; these poles will map to an area inside the unit circle in the z-domain. Figure 2 below illustrates the mapping of the j-omega axis onto the unit circle.

**Figure 2 – S to Z Plane Mapping**

The frequencies are warped due to the mapping from the s to z plane. They are essentially bunched together with the z-plane related to the s-plane by the function shown in equation 1 above. The ends of the j-omega axis meet at pie radians in the z-plane, this also happens to be half of the sampling frequency. One can tell if the filter will be inherently stable by solving the upper and lower quadratics (finding the poles and roots) and plotting them within the z-plane. If the complex vector’s magnitude is less than one, it lies within the unit circle. This means one can expect a stable filter. This is due to the fact that the left half s-plane maps directly within the unit circle in the z-plane.

The first step in deriving at the proper bi-quadratic coefficients using the bi-linear z-transformation is to start with an analog prototype. The low-pass second order Butterworth prototype used in the excel tool for the low and high pass filter coefficients, as seen below in equation 4. Equation 5 was used for the band-pass and band-stop prototypes.

**Equation 4**

**Equation 5**

Next the analog prototype transfer function needs to be de-normalized with one of the following transformations found below in equations 6, 7, 8, or 9. This is done by replacing “s” in the analog prototype with one of the below transformations. The Low-pass to Low-pass and Low-pass to High-pass transformations were used with the second order prototype. The Low-pass to Band-pass and Low-pass to Band-stop transformations were used in the first order prototype. Notice the omega prime term comes from the frequency warping function found in equation 1 above.

**Equation 6**

**Equation 7**

**Equation 8**

**Equation 9**

The Band-pass and Band-stop functions have two new terms. These can be found in equations 10 and 11 below. These come from the frequency warped band width of the desired filter we want to create. Once all the substitutions are made, the final z-transformation can be applied by subbing in equation 12 for s. Use some algebraic manipulation by multiplying the top and bottom of the z-transfer function by the highest negative order of z to obtain a bi-quadratic transfer function similar to the one found above in equation 3.

**Equation 10**

**Equation 11**

**Equation 12**

These values can also be obtained by use of the attached excel tool, or by way of one’s favorite scientific computing program. Once the coefficients are found, simply convert the values to binary signed fixed point “2.30” format. This means that the two most significant figures hold the values -2 to 1 and the 30 remaining bits are the positive fractional portion. Examples can be found in the following section

## Application

### Building the Circuit

The IIR filter module uses the following:

• 3-bit counter for enable flag synchronization

• 5, 32-bit IIR coefficient registers

• 2, 2-stage delay lines (feed-forward and feedback)

• 2 state, state-machine for synchronizing math operations

• 20/10 parallel multiplies (32 x 32-bit/32 x 18-bit)

• 64 to 32-bit and 50 to 18-bit truncation blocks (32 x 32-bit/32 x 18-bit)

• Summation stage, two additions and two subtractions in one clock cycle

• 32-bit to 18-bit truncation block for output to DAC

### Instantiating the IIR_Biquad.vhd Filter Module

The IIR filter is easily instantiated by including the IIR_Biqhad_xx.vhd file in a project and either port mapping the top level ports in Xilinx ISE or using a schematic file to connect to the ports. After creating a schematic symbol within the processes tab, the ports can be connected by adding wires within the schematic editor. The top level schematic can be seen in figure 3 below.

**Figure 3 – Xilinx ISE Schematic Top Level**

This application was run at 100MHz with plenty of slack for running faster speeds. The coefficients can be chosen in a variety of ways to include scientific computing programs, and manual calculations using the method of pole-zero placement, the matched z-transform, and the most popular method being the bi-linear z-transform approximation (as seen above in the background section). Included is an excel file that uses the bi-linear z-transform to generate bi-quadratic coefficients for low-pass, high-pass, band-pass and band-stop IIR filters. Once the coefficients are calculated, they will need to be converted to binary signed fixed point format “2.30”. This will produce numbers between -2 and 1.999999999068677…

To do this simply multiply the fraction by 2^30, enter the integer portion of the number into a calculator capable of converting large binary numbers, and convert. The portion converted will be the fractional portion of the coefficient. Next simply figure out the whole number portion between -2 and 1. If the coefficient is negative, find the difference of 2 and the coefficient. This gives us the positive portion (the fraction) that when added to the most significant bit (-2) gives us the original negative coefficient we desire. Examples of this conversion are found below in figures 4 and 5.

**Figure 4 – Binary Signed Fixed Point 2.30 Conversion Example 1**

Often times the coefficients turn out negative, in the case where a negative coefficient is needed, see figure 5 below for a conversion example.

**Figure 5 – Binary Signed Fixed Point 2.30 Conversion Example 2**

After the coefficients have been converted, enter them in place of the pre-existing coefficients in the IIR_Biquad VHDL module, synthesize and test the module.

### Hardware Test and Verification

The module was thoroughly tested through the use of Xilinx’s simulation software, ISim. A basic timer-driven two-state, state machine controls enable flags for synchronizing the math operations, truncating intermediate operations, and latching in the output each sample period. Each sample period advances the delay lines and starts the flag state machine. Each was tested in ISim. An ISim simulation screenshot can be seen below in figure 6.

**Figure 6 – ISim Simulation Screenshot**

The hardware was tested through the use of an LM4550 audio CODEC. A number of filters were created and tested by both introducing contentious 18-bit signals from 0 to 24 kHz and a single impulse to attain the filter’s impulse response. The impulse response then was subject to a Fast Fourier Transform to gain access to the filters frequency response. The first filter created was a 60 Hz second order IIR Butterworth Notch filter. An analog filter, 60 Hz Twin T Notch, was created to compare and contrast with the digital implementation. The digital IIR filter implementation would naturally suffer from a large amount of group delay due to the tight constraints. The frequency spectrum outputs from both analog and IIR digital filters can be seen below in figures 7 and 8. Both filters had stop-band attenuation well into the noise floor. Larger attenuation could be realized if larger input test signal were to be used.

**Figure 7 – 60 Hz Analog Twin T Notch Filter**

**Figure 8 – 60 Hz Digital IIR Butterworth Notch**

The analog filter suffers from thermal drift and frequency imperfections due to the discrete components required for the design. The digital IIR filter’s center frequency appears to be right-on with a small amount of roll-off at DC. The s and z-domain transfer functions for each filter can be seen below in equations 13 and 14 respectively.

**Equation 13**

**Equation 14**

We can determine the zero and pole placement by solving the numerator and denominator quadratics. In this case both are complex and can be seen below in equations 15 and 16.

**Equation 15**

**Equation 16**

The pole/zero plots for both analog and IIR notch filters can be seen in figure 9 below. Notice how the filter is on the edge of stability in both implementations.

**Figure 9 – Pole/Zero Plots for Both Analog and IIR Notch Filter Implementations**

Several example oscilloscope shots can be seen below. These tests introduce an impulse to the filter. The impulse response, seen in blue, is then subject to the FFT function on the scope; the filters frequency response is recreated in red. A 7 KHz band pass filter with a fairly large Q can be seen below in figure 10.

**Figure 10 – 7 KHz, Band Pass Implementation**

A second-order Butterworth derived band-stop filter can be seen below in figure 11.

**Figure 11-- 2.7 KHz, Band Stop Filter Implementation**

Another IIR implementation can be found in figure 12. This filter uses 3 bi-quadratic Chebyshev sections cascaded together for larger stop-band attenuation and a smaller transition band.

**Figure 12 – 8 KHz, Low-Pass, Chebyshev IIR Implementation**

## Capabilities, Limitations and Alterations

This reference design utilizes a Xilinx Spartan 6 development board and a National (by Texas Instruments) LM4550 audio CODEC. The design was developed in Xilinx ISE ver13.1. The Audio CODEC in this design is not required. The design can be scaled to many non-audio applications, not limited to a 48 KHz sampling rate.

## Conclusion

This reference design illustrates how one can use a drop in IIR filter along with a tool for calculating bi-quad coefficients to quickly filter a data stream in an FPGA. This design was targeted and tested in audio applications, although the design can be scaled down for a faster filter with less resolution. The fundamentals of IIR filter design have also been covered.

## Additional Information

Further DSP topics and filter design information can be found in the online book: The Scientist and Engineer’s Guide to Digital Signal Processing, By Steven W. Smith Ph.D. http://www.dspguide.com

Any questions regarding this eeWiki article can be directed to the author:

## Appendix: Downloads

The complete, IIR Filter Design in VHDL Targeted for 18 bit, 48 KHz Audio Signal Use, VHDL files and Excel IIR design tool can be downloaded here.

IIR_Filter_Coef_Generator.xls (33 KB)

IIR_Biquad.zip (2.1 MB)