FIR Filter (top level file): fir_filter.vhd (3.3 KB)
Data Types (must also be included in project): types.vhd (1.8 KB)
- VHDL source code of a FIR Filter component
- Configurable size of data input
- Configurable size of coefficient inputs
- Configurable number of taps
This details a FIR Filter circuit, written in VHDL for use in FPGAs. The component reads in a data stream and filter coefficients from user logic over a parallel interface and outputs the filtered result. It was designed using Quartus Prime, version 17.0.0. Resource requirements depend on the implementation. Figure 1 illustrates a typical example of the FIR Filter integrated into a system.
Figure 1. Example Implementation
A finite impulse response (FIR) filter has an impulse response that settles to zero within a finite period. They are inherently stable and require no feedback.
The output of a discrete-time digital implementation is a weighted sum of the most recent input samples. As such, it is defined by the convolution calculation:
The FIR Filter evaluates the convolution function given above using the architecture represented in Figure 2. It looks at the current input value (presented on the data port), and N previous values (for a total of N +1 taps). These values are shifted in on each system clock and subsequently shifted through a data pipeline.
The FIR Filter also clocks in and stores the coefficients presented on the coefficients port array. These values define the relative weight the filter gives to data samples.
Each coefficient is multiplied by the corresponding data sample. The filter then adds the resulting products to yield the final output result.
Figure 2. Architecture
The FIR Filter is configured by setting the constant parameters in the types.vhd file. Table 1 describes the parameters. These constants are used to define the data types that comprise the ports, internal pipelines, and internal arrays.
Table 1. Constant Descriptions
Table 2 describes the FIR Filter’s ports.
Table 2. Port Descriptions
The reset_n input port must have a logic high for the FIR Filter component to operate. A low logic level on this port asynchronously resets the component. During reset, the component clears its internal registers and the output result port. All input ports are ignored until the reset_n port again goes high. Once released from reset, the FIR Filter operation immediately resumes. Since the internal data pipeline was cleared, the initial output does not include all of the FIR Filter terms until enough input samples have shifted in to fill the pipeline.
This FIR Filter is a programmable logic component that executes a discrete convolution operation. The size of the input data, the size of the coefficients, and the number of taps for the filter are all configurable.
Comments, feedback, and questions can be sent to email@example.com.