RAM (VHDL)

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ram.vhd (2.4 KB)

Features

  • VHDL source code of a single port RAM component
  • Configurable memory size
  • Configurable width of each data word
  • Synthesizes into the internal memory block resources of most FPGAs

Introduction

This details a single port RAM circuit, written in VHDL. This memory component outputs data from the memory address specified and also writes input data to this address if a write enable is asserted. It was designed using Quartus Prime, version 17.0.0. Resource requirements depend on the implementation. Figure 1 illustrates a typical example of the RAM integrated into a system.

block_diagram

Figure 1. Example Implementation

Architecture

This RAM uses a write-before-read architecture. During a write cycle, the RAM writes the data before reading it on the output port, so the data shown on the output port is the same as that being written, rather than the old data that is being overwritten.

Configuring the RAM

The RAM is configured by setting the GENERIC parameters in the ENTITY. Table 1 describes the parameters.

Table 1. Generic Descriptions

Port Descriptions

Table 2 describes the RAM’s ports.

Table 2. Port Descriptions

Conclusion

This programmable logic RAM is a simple, single port memory component that outputs data from the specified memory address and, if a write enable is asserted, writes input data to this address. The number of memory locations and the data width are both configurable.

Contact

Comments, feedback, and questions can be sent to eewiki@digikey.com.