Logic issues with DE-10 Nano pins

I currently have a terasic DE-10 Nano asn some of my pins on JP junction 7 and 1 are stuck on either logic high or logic zero. Is there anything I can do about this?


Assuming you’re not talking about the supply pins present on those headers, such behavior would tend to be the result of either a programming error or hardware fault.

To say that there’s a million different reasons that a pin might not wiggle is probably a literal understatement in context of FPGAs. If you and the board/software are both new to each other, some sort of configuration/code error is very likely.

On the other hand, if you’re both well-acquainted and you can therefore be quite sure that you’ve used all the proper incantations and rituals required to charm the pins in question, then it’s possible that the device has experienced damage due to ESD or similar stress and is damaged beyond repair.

Thank you for you response. I have done all things I know in my knowledge capacity to figure it out. Whenever I call the JP junctions to be used certain pins not VCC give me a high. And other are low after a code is inputted when I expect a high. And me and the board are not that well acquainted, be were well on our way.