Minimizing EMI Problems in Noisy Switching Converter Circuits ...and Bears

Emissions From Switching Converters

Most products have to pass some sort of conducted emissions tests and radiated emissions tests. These tests usually occur at an EMC laboratory using a specialized set up as defined in the controlling standard. These labs are usually very expensive to use, often costing hundreds of dollars per hour. No one likes to get stuck at an EMC lab burning through a thousand dollars a day trying to put a magic band-aid on a fatally flawed design. It’s tough to go back and explain to one’s boss that only now, at the end of the design cycle, has it become clear that the design is insufficient and some major component must be changed. Most engineers would rather take a beating than have to admit such a failure.

Beyond the regulatory requirements there is the question of product reliability. Products that go into particularly hostile electromagnetic environments may require greater immunity to electromagnetic interference than the regulatory standard itself requires. This has been the author’s experience at two different companies.

With regard to emissions, most switching converters have two trouble areas that need to be considered up front. These two problem areas are: current loops in which the current changes very quickly (i.e. a fast di/dt) and nets in which the voltage changes quickly (i.e. those with a fast changing dv/dt)*. We will consider both of these problems.

What about the bears? Read on.

Example 1: The Flyback Circuit dv/dt problem

Here’s a common circuit many will recognize.

As can be seen in the image the drain net is the “noisy” high dv/dt net. This is easy to see in practice. Just turn the circuit on and hover an oscilloscope probe over Q1. Even at quite a distance the scope probe will pick up switching noise. One doesn’t even have to hook up the ground lead to the circuit. The oscilloscope can be totally unconnected to the circuit in question and still show the effects of the electric fields arising out of this noisy net. How does one deal with this problem? Generally, when designing a flyback circuit, reducing the area of this net to the maximum extent possible will help. Place the FET, Q1 as close as possible (almost touching) the pin of the transformer, L1. Since I = C*dv/dt and dv/dt is unavoidable, reducing C is about the only thing you can do to reduce the noise currents for free (i.e. without adding more parts), and without slowing the switching speed, reducing the efficiency of the converter, and generating more heat that has to be dissipated. As most EEs will recall the capacitance of a net is proportional to its area. Reduce a net’s area and its capacitance to the outside world will be reduced as well.

Is this really a big problem? Oh yeah, it’s a serious problem! The author has seen designs of this type that have 30V peak to peak of high frequency noise running into the load and preventing all communication between the major parts of a system. How does this net cause severe problems? Look at the picture below.

The transformer parasitic capacitances, C2 and C3 (especially C3), allow dv/dt noise from the primary side to drive currents on the secondary. This noise has to find a return path to the source. This isn’t always a problem. It is only a problem if it picks a return path that carries it to the outside world either through radiation or through the line impedance stabilization network (LISN) during the EMC test. Which brings us to an important principle.

Noise is not a problem. Noise is only a problem when it goes somewhere it shouldn’t.

At this point the reader may be thinking, “Hey, my design looks just like that, but maybe I’ll get lucky and my noise currents will pick a safe path back to the source”. Trust the author when he says you won’t be lucky. The only luck involved in EMC testing is bad luck. This brings us to the second principle:

Sans any prior planning, noise will always go where it shouldn’t.

This is true of many things: loud rock music, toddlers, grizzly bears, poison ivy etc. Take grizzly bears… Almost nobody has a problem with grizzly bears. They can growl, roar, eliminate wastes, eat small furry things and no one cares. …as long as they stay in the forest. However, if the bears go somewhere they shouldn’t like a golf course, difficulties arise almost immediately. Nobody wants to play golf with bears roaring, growling, eliminating waste on the greens, and chasing men in funny pants while you are trying to tee off.

In the figure below we have an example of “bears on the golf course”. The noisy dv/dt net is driving currents through the transformers parasitic capacitances and onto the secondary where they shouldn’t go. As you can see in the image, this is what the author usually calls: “BAD”. These currents may go out into the load which may inadvertently pass them onto an unsuspecting cable or the metal frame of your product. Either of these eventualities can potentially lead these currents to use the ground lead of your product (and consequently the LISN) as part of its return path to the source. Though I haven’t drawn this path (yet), noise on the ground line is what one might call “VERY BAD”.

So, since we know where the noise comes from, we just have to give it a return path that doesn’t pass through the golf course EMC measuring instrumentation. Unlike grizzly bears, high frequency noise is quite easy to lead around safely if one plans for this eventuality during the schematic design phase. As mentioned earlier, the EMC test phase is often too late. If the bears are loose at that point, the design may be doomed until the designer goes back and changes the schematic and layout.

Anyway, in the “GOOD” figure above you can see that a capacitor, C4 has been added. C4 is a real (not parasitic) capacitor. More specifically it is a Y type safety capacitor (i.e. P10743CT-ND ) that provides a benign return path for high frequency noise currents that pass through the transformer’s parasitic capacitance. This path avoids the LISN and most common unintentional antennas. Try to keep the current loop formed by C3/L1, C4, and Q1 as small as possible. Often an SMT Y-cap can actually fit under the transformer. The loop can’t get any smaller than that.*** Many contract manufacturer (CM) will scream and gnash their teeth at the suggestion of stacking components this way, but just tell the CM to “stop crying and deal with it”. Many times the CM is worried about rework. If the capacitor fails they’ll have to remove that big transformer to replace the cap. That’s great and all, but the author has never ever heard of a Y-cap failing during assembly. If it’s a double sided board you could put this cap on the bottom as well. However, the author doesn’t like double sided boards. On this point, the author and most CMs agree. All that said, often placing the cap right beside the transformer is good enough. One other point before moving on, any noise currents passing through the other lead of the secondary winding will likely pass through D1 and C1 and then return to the source through C4 as well.

In the image above, a slightly different implementation is shown. In this version, a common mode choke (i.e. 553-1402-ND) has been added to the output of the flyback. This can be useful if lower frequencies are are problematic. At very high frequencies, noise currents are more likely to take the lowest inductance path back to the source which will usually be C2. The path out into the load, onto the frame (or a cable), down the ground lead, through the LISN and back through the front end of the system is likely to be a much higher inductance path than just running back through C2. However, at lower frequencies (i.e 100s of kHz to a few MHz) the choke may be useful. Or if the design engineer has to meet a very stringent EMC standard such as medical or some military standard this may be necessary as well.

Example 2: The Flyback Circuit di/dt problem

Earlier it was mentioned that there are two general types of problems: dv/dt problems and di/dt problems. “dv/dt” problems usually drive currents through capacitive coupling as discussed in Example 1. “di/dt” is a problem in itself. If these fast changing currents or associated harmonics get out into the environment problems can result. Additionally, “di/dt” often can couple through magnetic fields. As we all know, electric currents give rise to magnetic fields. Generally speaking the primary currents we have to worry about with regard to EMI and EMC are very fast changing di/dt events. The flyback circuit has several fast changing currents to be concerned about. Consider the schematic given below.

Of the four currents shown, the one most often causing problems (in the author’s experience) is “Iout”. This current has a nearly right triangle shaped waveform with a very fast turn on time. This loop’s area should be minimized as much as possible in order to minimize rapidly changing magnetic fields. All the currents shown should have their loop area minimized, but for the purposes of this article the focus will be on the output current.

To reduce the size of this loop there are a few obvious things one can do. Place D1’s anode “as close as possible” to T1’s pin. Place D1’s cathode “as close as possible” to C1. How close is “as close as possible”? As close as one can put it without having the CM refuse to manufacture the PCB. See the example below:

In the image the dotted lines show the return trace on the next lower layer of the PCB below the top routing layer that has the pads of D1 and C1 on it. By staking the outgoing and returning traces on top of each other the loop area is minimized down to nearly zero.

In addition to “Iout”, “Igate” occasionally causes problems as well. Generally speaking keeping the loop area of this trace as short as possible and making sure Rgate is of sufficient size to keep the net’s rise and fall times under control is all that’s needed.

Example 3: The Buck Converter

Now let’s move on the the so called “buck” converter topology. Where are the dv/dt problems in the figure below?

Yes, that’s right. The inductor/diode/FET net is the high dv/dt net (see below). As mentioned before, minimize the area of this net to reduce its coupling to the outside world.

What about problematic di/dt loops? See below:

This isn’t the only current loop in this circuit, but often it is the most problematic.This loop has very fast changing currents, particularly the leg with the diode in it. This part of the loop goes from zero to full current very very quickly when Q1 turns off. At the beginning of the cycle Q1 is switched on to drive current through L1 thus storing energy in its magnetic field. This current flows through Q1, L1 and the caps. D1 isn’t involved. When Q1 is switched off, L1 won’t allow the current to stop if there is any possible way to keep the it going. D1 provides such a way (path) to keep the current flowing. For example, if Q1 is turned on and the current through L1 and Q1 ramps up to 1A and then the Q1 is switched off in say 50ns. The current through D1 then goes from 0A to 1A in 50ns. That’s a pretty fast di/dt! Route this net carefully.

Some controllers put D1 (maybe Q1 too) inside the IC itself. For example, take a look at MCP16321/2 from Microchip or ADP2442 from Analog Devices:

This is a good thing from an EMC standpoint generally. If you can use a part such as this it may save you some trouble with regard to EMC. It allows you to keep loop areas much smaller than would otherwise be possible using discrete diodes and FETs. As long as we’re on the subject of discrete components, some designs use another FET instead of D1 to improve efficiency. These are “synchronous” buck converters because they have to synchronize the switching of the two FETs to maximize efficiency and to prevent shorting Vin to ground by having both FETs on at once. However, the current loops and the topology are the same.

Example 4: The Boost Converter

Shown in the figure above is the boost topology in all its glory. It’s a great circuit that finds uses in lots of different applications. Some more likely to make noise than others. Take for instance the power factor correction circuit (PFC). In its boost configuration this is a fascinating circuit, but if I may analogize again, it is a grizzly bear theme park. The bears in this park are always trying to escape. To continue, in the typical PFC circuit the input voltage can (at regular intervals) reach upwards of 170V peak in the United States. In Europe where line voltages are around 220V the peak voltage can get much higher, over 300V. So if Q1 is switching at 100kHz (a conservative estimate) the net labeled in the figure as a “fast dv/dt” is essentially a 320V clock signal with really fast rise times. This isn’t just bears loose on a golf course, this is like 10,000 bears all hopped up on narcotics running loose in the Mall of America. Even using all our techniques of fast dv/dt net area minimization, current loop minimization, Y-cap placement, and common mode choke usage don’t be surprised at EMC testing if there are still a couple of hundred bears running loose in the mall food court. …you’ve been warned. Try to keep the frame of your product as far from this circuit as possible. Don’t run any cables near it. You might even need some shielding over it.

Even if you do all this right there is still a big looming problem. Q1 is likely to need a grounded heat sink. Gag, grounding the heat sink means Q1’s drain (the noisiest net in the system) is going to be capacitively coupled directly to the ground lead. Sounds like a disaster, but there is hope.

Example 5: System Level Noise Current Steering

Now we move on to the big picture, or at least what one might call the system level picture of an EMC test. One point to keep in mind, though it is drawn separately in this case, L1 (below) would normally be on the same PCB as the “noisy system”. As mentioned before, the “LISN” is a measurement device that the EMC lab (or the designer) will use to measure how much noise the new product will drive out into the world to interfere with other peoples cell phones, TVs, stereo systems, and pacemakers.

In this “big picture” view, the drawn arrows represent noise currents (bears) generated in the system. …possibly by the flyback circuit. The capacitors labeled “Cp” represent parasitic capacitances. The noise currents are trying to find a way back to their source in the “noisy system”. Any time noise currents go into the LISN, failure is often the result. This technique requires a very large common mode choke. It literally needs to “choke” off the noise currents. This is the brute force method. Like using an 8 inch howitzer to hunt bears. It’ll work, but there is an easier, cheaper way.

In the figure above, the drawn lines represent the same noise generated currents, and again, some “Y” type safety caps are used to provide a return path that doesn’t involve the LISN. Additionally, the loop area is kept smaller. The currents follow a short lower inductance path. Using this technique, L1 can generally have a lower inductance than in the “BAD” case above. This usually means it is physically smaller and less expensive too. There is still a small risk that these loop areas could be big enough to cause radiation, but it is a smaller risk than letting the currents run out the cables and through the LISN. Instead of using an 8 inch howitzer to stop the bears, a bolt action rifle is used. It’s cheaper, easier to carry around, and the reader won’t have to ask other people to help load it.

Just as an example, let us suppose that the most troublesome noise current is measured to be 300kHz (that’s a pretty slow bear). If only one 4.7nF Y-cap were used for Cy and a 1mH inductor were used for L1, their relative impedances at 300kHz are**: ZL = 1884 Ω, ZC = 112 Ω Obviously, very little current will choose the path through the LISN and ZL as in the “BAD” example. Most of the noise current will flow through the “Y” cap, ZC as in the “GOOD” example. Even if a relatively small 100uH choke were used, ZL is still pretty sizeable (188 Ω). So we see that Y-caps allow the use of much smaller common mode chokes. Y-caps are the way to go. As may be expected, this effect only gets more pronounced as the frequency increases. Which leads us to another principle:

High frequency noise currents are easier to reroute or attenuate than low frequency currents.

What if we have a relatively fast 10MHz noise signal? Now ZL = 6280Ω, ZC = 3.4Ω Oddly enough, the faster the bear is, the easier it is to lead around.

*Some EMC experts would correctly point out that all EMC problems arise out of current. They would say that only di/dt matters. So called “dv/dt” is just a side effect of current. However, from the point of view of the average circuit designer this distinction is primarily a semantic one. Some purists may not like it, but this article will still refer to dv/dt because it is a useful concept that all electrical engineers understand easily and can prove useful in finding trouble spots within a design.

**ZL = jωL and ZC = 1/jωC

***…The return could be smaller without placing shields inside the transformer itself.