APDahlen: could you describe that effort? What do you mean by a stiff rail bypass? Just a fat cap like 10uF or more? Or a diversity of caps to handle various frequencies?
I guess I could inject some zeros and poles with various caps… (thinking root locus now…) see what happens. But I am thinking its not oscillator related, because it blows when I do polarity reversal on Vgate-drain… or simply just pulling gate down and back up with generous delay between steps.
Yes, diversity!
At first the oscillation problem was continuous. As capacitors were added the result was a damped oscillation (ringing) on a step (square wave) disturbance. Later as the rail was properly bypassed, the problem was eliminated.
As for diversity, it was a textbook application, a large electrolytic for the rail with small (0.1 uF) close to the transistor. The large cap for bulk storage while the small cap to bypass high frequencies. This is done with the understanding that the large electrolytic cap starts to look like an inductor at high frequencies.
As for testing, recommend dual channel oscilloscope: one channel to trigger and the other to observe. For example, trigger on falling gate signal and observe the drain. Then trigger on rising gate again monitoring the drain. A storage scope is necessary at the signals are very difficult to see with an analog scope. Gone are the days of oscilloscope light shields and polaroid film - thank goodness.
Thank you for your patience. As @rick_1976 stated “I advise holding manufacturing defect as a theory of last resort, not to be wielded without a large volume of supporting evidence.” You are certainly developing that case.
Is this an accurate summary of your situation:
MOSFETs are installed in old equipment. Here the term old implies that the boards have been in service without problems for an extended period of time.
Other similar MOSFETs are used successfully in the application. Part number and manufacturer unknown.
A single batch of DIGIKEY purchased DMN67D8L-7 MOSFETs do not operate in the old equipment. Specifically, the MOSFETs are unable to handle a negative V_GS. This includes a voltage as low as -12 VDC for a device rated at +/-30 VDC.
Troubleshooting as outlined in this thread with the most significant experiment being conducted in a 12 VDC system.
Schematic as shown in this note with the mentioned concerns including relationship between gate and resistors and capacitor.
Oscilloscope reading to be taken tomorrow.
Sincerely,
Aaron
Thank you for your thorough response. I’ll do a thorough test tomorrow with my scope and following your recommendations. I just wanted to mention the following, I see that you said other mosfets were used successfully in the application but no part #:
Here’s a couple mosfets I commonly use. They are SOIC-8 packages and have an independent PMOS paired with the NMOS that I sometimes just don’t use. In this application they are unused.
FDS4559
AO4611
They are Vgs +/-20, but in those cases I use 12V at the gate. Outside of this application: They handle much dirtier scenarios too, relays and solenoids with no flyback, 24VDC motors that draw an amp with no flyback, no inrush protection, no bypass caps, DCDC conversion with high frequency, and I have never had one blow and some have been in the field for years.They are just tough suckers.
But our little buddy of interest just cant do anything haha
DMN67D8L-7
Did I mentioned some died with no load? just flipping gate and drain high and low breaks them?
I’ll do a full test tomorrow with a scope. Talk to you later.
Our issue with this mosfet that is dying is he is rated for +/-30Vgs and still dies at 12 which is inferior to these other two mosfets, and handles a measly 5mA and blows in a very sanitary circuit.
Hi @thomas.wright,
E.g. the AO device has 100 times bigger gate capacitance than the DMN thing so it probably is more resistant to parasitic transients.
As the failure occurs when the source load is grounded, it somehow suggests that there is a huge transient on source terminal, most likely caused by the long flat cable that is between the source and the load (LED). How long that cable is?
If you place a small (say 1nF) capacitor in parallel with the source switch, would you still get the snap, crackle and pop?
Cheers, heke
Has the top mark on the materials in question been validated (7D8)? Mis-picks do happen, and could explain the observed difficulties nicely.
Ok, here we go. Scope readings. Out of 24 lines I measured, about 4 of them produced this towering 70V spike. And, 1 of those blew.
Everything is 10v/div, 1ms/div
Top left pic is 70V peak spike on source side during turnoff. top right is a good line during source turnoff, bottom left is bonkers source turnoff, bottom right is a 40V gate warble; most gates were clean.
So, I guess I got unlucky. I’m trying to intellectualize why those particular lines are bad but as seen below, they are all quite similar to each other. And the lines producing bad voltage spikes are seemingly random. I circled 3 of the bad ones as an example which I had as numbers 2, 16, and 24. two are on the outer rim, ones in the center. There’s just no pattern but there’s an explanation for everything I guess.
I don’t have through hole caps that I can use to solder the source or drain lines to couple them to ground. But that will fix the issue by resisting dv/dt.
Those traces are 1oz,10mil traces, with 10mil spacing from each other. Then there are several inches of ribbon which heke suggested as a possible issue; though again its only a few lines doing this. Wouldn’t a majority of them do that? The other traces are super clean (like I expect), barely overshoots to 24.5V during transience.
===========
ribbon cables. When plugged into our tool it can be several feet of ribbon. I’m just suprised 5mA can make a 70V spike on select lines… this is still mysterious but I’ll add caps to it and just solve the issue.
We can mark this case closed. The mosfets are fine.
As Heke mentioned, the fets I usually work with do have much more built in capacitance. So that, we might say, is what snuck up on me was having not dealt with such a low capacitance fet before. gg
Hello Thomas,
We can’t thank you enough for posting this material. This is a perfect case study for things that can and do go wrong in seemingly simple circuits. It’s the theory vs practical side that is missing from the literature - the alignment of the stars of misfortune.
Know that I have pulled the components from DigiKey stock. My intention is to recreate these experiments and offer suggestion for our readers. With your permission, I will refer back to this excellent forum thread.
More to follow.
Sincerely,
Aaron
Hello!
Yes, feel free to use this as an example. And thank you very much for your assistance.
Hello @thomas.wright,
As a follow up. It took some time, but I did develop a series of articles exploring the MOSFET. Please consider:
Sincerely,
Aaron
