Porting Altera design to MicroSemi (SmartFusion2)


I have the VHD files for an IP, but not sure how to connect it to the logic… i.e, adding it to the project so that it’s visible to the Arm.

In the Altera world, it’s fairly easy… I’d create a Qsys component that uses the IP’s top-level signals, and then map each of the interface signals to the avalon bus (Reset, Clock, address and data). All other signals would get exported. Qsys would then generate a VHDL file of the system, with the exported signals exposed. In my HDL file, I would instantiate the Qsys object and connect its exported signals to other logic or output pins of the device. The Nios processor would access the IP just as it would any other memory-mapped peripheral.

I assume the flow for Microsemi, would be roughly the same, but haven’t figured out based on the Application Note (AC333). Is there any other document or example that shows how to do this?

Is there any training/webinar that would help with SF2?


Hello, let me see if I can find any additional information for you regarding this topic.


@sdr_luddite Have you looked at the get started guide we have on the eewiki for the Smartfusion 2?


If that doesn’t help let me know and I can get some more information for you.


The SmartFusion design flow is fairly similar to Altera’s, but less abstracted. There is no tool like Qsys to generate files for you. Instead you have to write the whole wrapper for your IP block and set up mappings from the AMBA bus to the internals of your IP. You can then instantiate the wrapped component in your schematic and connect it to the MSS through the appropriate bus.

The app note you mentioned is the best source I’m aware of for using custom IP with SmartFusion.