I have the VHD files for an IP, but not sure how to connect it to the logic… i.e, adding it to the project so that it’s visible to the Arm.
In the Altera world, it’s fairly easy… I’d create a Qsys component that uses the IP’s top-level signals, and then map each of the interface signals to the avalon bus (Reset, Clock, address and data). All other signals would get exported. Qsys would then generate a VHDL file of the system, with the exported signals exposed. In my HDL file, I would instantiate the Qsys object and connect its exported signals to other logic or output pins of the device. The Nios processor would access the IP just as it would any other memory-mapped peripheral.
I assume the flow for Microsemi, would be roughly the same, but haven’t figured out based on the Application Note (AC333). Is there any other document or example that shows how to do this?
Is there any training/webinar that would help with SF2?