Problem with "Getting Started w/ SmartFusion2" eewiki

Embedded Development Boards, Kits, Programmers
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1

I’m following the instructions here,

but getting errors like this, when I get to the step on adding/editing the constraint file:
“port name doesn’t exist in the netlist or is not connected to an IoCell macro at PDL Line : set_io MMUART_0_TXD_M2F - direction Output”

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This seems to suggest the UART IP isn’t getting mapped to the pins, however the UART is configured to Fabric (like the guide shows), and the Modem checkbox isn’t selected so not sure why it’s trying to map to an I/O. Also, the guide doesn’t specify to do any manual pin mapping, so I’m kind of lost on what could be the problem.

BTW, I’m using 11.8sp3.

2

Hello,

Thank you for your inquiry. We have gotten your questions and will be looking for a way to help answer those for you. Once we have an answer we will reply to this post.

Thanks, Bobby

3

Could you post a screenshot of your block diagram?

4

Just to make it simpler, I thought I’d remove all but a UART peripheral…

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The resulting pdc generated from the root module [target] shows:

set_io {DEVRST_N}
-direction Input

set_io {MMUART_0_TXD_M2F}
-direction Output

set_io {MMUART_0_RXD_F2M}
-direction Input

But still get the same error…

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5

@sdr_luddite,

Does this error only occur after synthesis or when running a specific process? I’m trying to reproduce it, but haven’t been able to so far. I have the same block diagram set up and the same .pdc and have no errors.

Microsemi’s docs suggest it’s an optimization issue, but it doesn’t seem like that would apply here: http://www.actel.com/kb/article.aspx?id=KI8821

6

It synthesizes fine, but it fails during either Place and Route, or doing a ‘Check’ in the Constraint Manger tab.

As a new user, looks like I’m not allowed to upload the file, so I’ve zipped the project folder and placed it here:
https://file.town/download/2cjzc9teuj6vunjrel85psv47

7

I’ve found some sort of a fix/workaround. I went into Project -> Project Settings -> Design flow and deselected “Enable block creation.” Hit Save in the top right corner. It will warn you that it will clear previous results from your design tools. After that I was able to re-run the design flow without errors.

My hypothesis is that there was a file somewhere that wasn’t properly updated and cleaning the work space fixed it. Re-enabling block creation after running the design flow successfully still worked.

2 Likes
8

Thanks that worked! I’m surprised no one has encountered this before.

I’ll continue with the rest of the eewiki and program the board, thanks for the help!

1 Like