Subtitle: Approach to Estimate Switching Time Intervals Using Datasheet Parameters
1. Introduction
In Part I of this series, equations were developed to calculate MOSFET turn ON and turn OFF switching time intervals. These time intervals form the basis for switching power loss calculations in hard switching applications.
When applying these equations, it becomes evident that additional guidance is required. Several
parameters used in the calculations, particularly gate plateau voltage and parasitic capacitances, depend strongly on operating voltage and current conditions. These parameters are not always directly available for the intended use case.
This application note provides practical methods to estimate these parameters using commonly
available datasheet information. Approaches for plateau voltage approximation, reverse transfer
capacitance extraction, and output capacitance modeling are presented. These methods enable
consistent comparison of MOSFET switching behavior across suppliers when detailed SPICE
models are not available.
The techniques described in this Part II are intended for component level comparison and early
stage device selection. When the objective is application-level loss modeling or worst-case
analysis, time domain simulation using validated SPICE models remains the preferred approach.
1.1 ON and OF time intervals
From Part I of this series, time intervals for the turn-ON transition are given as follows:
In addition, the turn-OFF transition time intervales were found to be:
Where \tau=R_{G}(C_{GS}+C_{GD}), the time intervals are defined as in Figure 1, and the following parameter definition apply:
- R_G: Gate resistance (internal and external).
- C_{GS}: Parasitic Gate-to-Source Capacitance.
- C_{GD}: Parasitic Gate-to-Drain Capacitance.
- R_{DS_{(ON)}}: Drain-to-Source resistance when MOSFET is fully-ON.
- V_{th}: Threshold Voltage.
- V_{gp-ON}: Plateau Voltage during ON transition.
- V_{gp-OFF}: Plateau Voltage during OFF transition.
- V_{GG}: Gate external voltage supply DC value.
- V_{DD}: Drain external voltage supply DC value.
- I_0: Drain load DC current.
Equations 1-6 were derived from a Low-Side Driver sample circuit with inductive load and ideal
recirculating diode as the one shown in Figure 2.
Figure-1. Turn-On MOSFET waveforms (Upper) and Turn-Off MOSFET waveforms (lower).
Figure-2. Low-Side Driver Sample Circuit
2. Parameter approximations
2.1 Plateau Voltage for ON and OFF stages
It is clear from equations 2-4 and 6 that Gate Plateau Voltage is a parameter of high importance.
However, deciding what voltage to use is often difficult.
Datasheet will show a Plateau Voltage under a determined set of conditions of Drain Voltage and Current. This value can be extracted from the datasheet Gate Charge plot to be used for
calculations (Figure 3).
Figure-3. Typical Gate Charge plot from Power MOSFET datasheet.
Nevertheless, conditions for measuring Plateau Voltage are not standard and therefore looking for an approximation that considers surrounding conditions makes sense.
According to [1] Plateau Voltage might even be different depending if the device is turning OFF or turning ON, and it will be defined by the following equations:
Where g_m is the transconductance obtained from the slope of the linear portion of the Transfer Characteristics (Figure 4).
Equations 7 and 8 are an option to derive Plateau Voltages for ON and OFF stages that bring
datasheet Plateau to closer reference conditions for parameter comparison of two or more Power MOSFET Part-Numbers.
Figure-4. Typical Transfer Characteristics Plot from Power MOSFET datasheet.
2.2 Reverse Transfer Capacitance (C_{rss})
From Part I of this series, we know that Reverse Transfer Capacitance C_{rss} is equal to C_{GD} which is a major parameter for equations 3 and 5. C_{GD} can be obtained by using Gate-Drain charge, Q_{GD}, from datasheet dynamic characteristic tables, which lets the following formula to be applied:
When using this method, it needs to be considered that Q_{GD} is obtained with a determined V_{GS} value different from zero and that C_{GD} non-linear capacitor is both dependent on V_{GS} and V_{DS} bias values (Figure 5).
Figure-5. Example of Gate-Drain Charge from Power MOSFET datasheet .
Another way of approaching this capacitance will let us have values obtained from a standard
method [3] that uses same measurement conditions making component comparison more trustable. C_{rss} characteristics plot, Figure 6, is obtained with a sweep of bias voltages for V_{DS} with added small signal v_{ds} high frequency disturbances (i.e. capacitances in Figure 6 are small signal capacitances). It is worth noting that is an industry standard to have V_{GS}=0V during this characterization.
Figure-6. Example MOSFET Small-Signal Capacitance plots from datasheet.
From this plot, we can read the C_{rss}=C_{GD} value to desired V_{DS} voltage and use it for time interval calculations. That is one valid way of doing it, sufficiently good for comparison purposes.
Alternative way is to find an equivalent linear capacitor value related to the charge on the non-linear capacitor at the desired V_{DS}. To do this, all points in the C_{rss} capacitance characteristics need to be extracted and used to simulate the non-linear charge curve with respect to its terminal voltages using the method in [2]. C_{GD} is then obtained applying formula (9). These last two methods allow us to have C_{GD} values for all MOSFETs in comparison that use the same V_{DS} and V_{GS} bias conditions.
This last simulation step can be regarded as an unnecessary extra step if the analysis goal is just to compare component performance. However, having this simulation allows detailing the non-linear capacitors more completely as is shown in Figure 7.
Figure-7. Non-linear capacitor charge curve (C_d – small signal capacitance at V_x, C_t – equivalent linear capacitor at V_x).
2.3 Output Capacitance (C_{oss})
Once C_{GD} is defined, the same approach can be taken for C_{DS}. In similarity with C_{rss}, Output Capacitance C_{oss} is defined in Figure 6 plot. Same benefit of having measurements with a well stablished method is accomplished, this makes conditions between suppliers similar and comparable.
The value of C_{DS} is obtained after applying the following subtraction:
Where, as was detailed above, C_{oss} can be read directly from the small signal non-linear
capacitance plot (Figure 5) or the points from this characteristic can be extracted to simulate the
non-linear charge curve with respect to Drain-to-Source voltage [2] and use:
2.4 Gate-Threshold Voltage (V_{th})
For this Application Note, typical Threshold Voltage defined from the datasheet is used. No
detailed calculation was found in the literature.
In addition, vendors typically use the same conditions (i.e. V_{DS}=V_{GS}, I_D=250 \mu A) for measuring this parameter which makes comparison easier (Figure 8).
Figure-8. Typical Gate-Threshold datasheet table.
3. Calculation example
3.1 Sample circuit
Taking the following values for surrounding conditions on Figure 1 Low-Side driver circuit: V_{GG}=10V, V_{GG}=75V, I_0=15A, R_{g_{ext}}=10 \Omega an example calculation will be presented here.
For this, MCC’s Power MOSFET MCAC15N15Y will be used along with two competitor MOSFETs that are close in electrical characteristics. Table 1 and Table 2 show these component parameters that are relevant for this analysis.
Table 1: Electrical parameters for MCAC15N15Y relevant for calculations.
| Parameter | Symbol | MCAC15N15Y | Conditions |
|---|---|---|---|
| Drain-Source Maximum Voltage | V_{DS} | 150V | V_{GS}=0V, I_D=250\mu A |
| Gate-Threshold Voltage | V_{GS{(th)}} | 2V to 4V | V_{DS}=V_{GS}, I_D=250\mu A |
| Drain-Source On-Resistance | R_{DS_{(on)}} | 52mΩ (typ) 70mΩ (max) | V_{GS}=10V, I_D=15A |
| Internal Gate Resistance | R_{gint} | 1Ω | f=1 MHz, Open drain |
| Gate-Drain Charge | Q_{GD} | 4nC | V_{DS}=75V, V_{GS}=10V, I_D=15A |
| Plateau-Voltage | V_p | 4.9V | V_{DS}=75V, I_D=15A |
| Input Capacitance | C_{iss}=C_{GS}+C_{GD} | 749.9pF | V_{DS}=30V, V_{GS}=0V, f=1 MHz |
| Output Capacitance | C_{iss}=C_{DS}+C_{GD} | 301.1pF | V_{DS}=30V, V_{GS}=0V, f=1 MHz |
| Reverse Transfer Capacitance | C_{rss}=C_{GD} | 27.3pF | V_{DS}=30V, V_{GS}=0V, f=1 MHz |
Table 2: Electrical parameters for competition that are relevant for calculations.
| Symbol | Competitor A | Conditions | Competitor B | Conditions |
|---|---|---|---|---|
| V_{DS} | 200V | V_{GS}=0V, I_D=250\mu A | 150V | V_{GS}=0V, I_D=250\mu A |
| V_{GS(th)} | 2V to 4V | V_{DS}=V_{GS}, I_D=1mA | 2V to 4V | V_{DS}=V_{GS}, I_D=35 \mu A |
| r_{DS_{(on)}} | 86mΩ (typ) 102mΩ (max) | V_{GS}=10V, I_D=12A | 42mΩ (typ) 52mΩ (max) | V_{GS}=10V, I_D=18A |
| R_{gint} | 1.1Ω | f=1 MHz | 2.1Ω | f=1 MHz |
| Q_{GD} | 10.1nC | V_{DS}=100V, V_{GS}=10V, I_D=12A | 1.5nC | V_{DS}=75V, V_{GS}=10V, I_D=9A |
| V_p | 4.5V | V_{DS}=100V, I_D=12A | 5.2V | V_{DS}=75V, I_D=9A |
| C_{iss}=C_{GS}+C_{GD} | 1568pF | V_{DS}=30V, V_{GS}=0V, f=1 MHz | 670pF | V_{DS}=75V, V_{GS}=0V, f=1 MHz |
| C_{oss}=C_{DS}+C_{GD} | 170pF | V_{DS}=30V, V_{GS}=0V, f=1 MHz | 80pF | V_{DS}=75V, V_{GS}=0V, f=1 MHz |
| C_{rss}=C_{GD} | 55pF | V_{DS}=30V, V_{GS}=0V, f=1 MHz | 3.4pF | V_{DS}=75V, V_{GS}=0V, f=1 MHz |
3.2. LTspice simulation of sample circuit
Simulations using SPICE models from MCAC15N15Y and Competition were performed. From simulation results measured time intervals t_{ON}=t_{{21}_{ON}}+t_{{32}_{ON}} and t_{OFF}=t_{{21}_{OFF}}+t_{{32}_{OFF}} are going to be used in this analysis as a reference. Results are shown in Table 3. Figure 8 shows t_{ON} measurement from simulations taken from the point where the 5% of maximum Drain current is reached (0.05\ast I_0=0.75A) to the point where 5% of the maximum Drain voltage is reached (0.05\ast V_{DD}=3.75V). Same points, but with voltage appearing first than current were taken to measure t_{OFF} (Figure 9).
Table 3: Turn-on and turn-off times obtained from simulation measurements.
| MCAC15N15Y | Competitor A | Competitor B | \Delta MCC - A | \Delta MCC - B | |
|---|---|---|---|---|---|
| t_{ON}=t_{{21}_{ON}}+t_{{32}_{ON}} | 8.68ns | 18.40ns | 5.46ns | -9.72ns | 3.22ns |
| t_{OFF}=t_{{21}_{OFF}}+t_{{32}_{OFF}} | 12.43ns | 23.00ns | 5.91ns | -10.57ns | 6.52ns |
Figure-9. MCAC15N15Y Turn-on time from Simulation (I_0 in green, V_{DS} in dark blue & V_{GG} in light blue.
Figure-10. MCAC15N15Y Turn-off time from Simulation (I_0 in green, V_{DS} in dark blue & V_{GG} in light blue.
3.3. Calculating using datasheet values
Calculations using datasheets values shown in Table 1 and Table 2 were used to calculate results in Table 4.
Table 4: Calculation results using datasheet values.
| MCAC15N15Y | Competitor A | Competitor B | \Delta MCC - A | \Delta MCC - B | |
|---|---|---|---|---|---|
| t_{{10}_{ON}} | 2.94ns | 6.26ns | 2.91ns | ||
| t_{{21}_{ON}} | 2.61ns | 4.24ns | 3.08ns | ||
| t_{{32}_{ON}} | 4.37ns | 8.26ns | 2.02ns | ||
| t_{ON}=t_{{21}_{ON}}+t_{{32}_{ON}} | 6.98ns | 12.49ns | 5.1ns | -5.51ns | 1.88ns |
| t_{{10}_{OFF}} | 5.89ns | 14.02ns | 5.33ns | ||
| t_{{21}_{OFF}} | 4.55ns | 10.09ns | 1.87ns | ||
| t_{{32}_{OFF}} | 4.05ns | 7.12ns | 4.48ns | ||
| t_{OFF}=t_{{21}_{OFF}}+t_{{32}_{OFF}} | 8.60ns | 17.21ns | 6.35ns | -8.61ns | 2.25ns |
3.4. Calculation using Plateau Voltage
Modeling approach of Plateau Voltage described in Section 2.1 was used to obtain results shown in Table 5.
Table 5: Calculation results using Plateau Voltage model (Section 2.1).
| MCAC15N15Y | Competitor A | Competitor B | \Delta MCC - A | \Delta MCC - B | |
|---|---|---|---|---|---|
| t_{{10}_{ON}} | 2.94ns | 6.33ns | 2.91ns | ||
| t_{{21}_{ON}} | 1.22ns | 1.35ns | 1.80ns | ||
| t_{{32}_{ON}} | 3.69ns | 7.00ns | 1.73ns | ||
| t_{ON}=t_{{21}_{ON}}+t_{{32}_{ON}} | 4.91ns | 8.35ns | 3.52ns | -3.44ns | 1.39ns |
| t_{{10}_{OFF}} | 8.60ns | 18.78ns | 8.99ns | ||
| t_{{21}_{OFF}} | 6.32ns | 13.23ns | 2.92ns | ||
| t_{{32}_{OFF}} | 1.33ns | 2.36ns | 0.82ns | ||
| t_{OFF}=t_{{21}_{OFF}}+t_{{32}_{OFF}} | 7.65ns | 15.59ns | 3.75ns | -7.94ns | 3.90ns |
4. Conclusions
Comparing switching performance of different Power MOSFET vendors or even same vendor Power MOSFET part numbers is always a challenge. Measurement conditions affect MOSFET parameters and this consequently affects any performance prediction.
However, in this application note we show that using Datasheet values or additional modeling approach of Plateau Voltage gives good results when targeting comparison, both will give a good approximation of how slow or how fast one component is against the other.
Delta comparisons between components using both approaches will give a good indication of how switching performance will perform when both are used under same conditions. Nevertheless, using the modeling approach of Plateau Voltage presented here will bring all comparisons to the same point of reference which is an added benefit if available specification of Plateau Voltage was taken under completely different conditions.
You can also check this Application Note: Quick Guide for Power Losses Calculation in MOSFETS – Part 2 and the first part Application Note: Quick Guide for Power Losses Calculation in MOSFETs - Part 1 in our website. The third part, on which we will be showcase the full power losses calculation for this circuit will be released soon.
Bibliography
- Liu, S., Song, S., Xie, N., Chen, H., Wu, X., & Zhao, M. (2021). Miller Plateau Corrected with Displacement Currents and Its Use in Analyzing the Switching Process and Switching Loss. Electronics 2021 , 10
- Ben-Yaakov, S. & Zeltser, I. (2017). On SPICE simulation of voltage dependent capacitors. IEEE Transactions in Power Electronics
- JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (1985)](https://www.jedec.org/system/files/docs/jesd24.PDF). JESD24 JEDEC Standard for Power MOSFETs