I am currently having problems testing external loopback testing with the QSFP ports on the VPK120. I have read through many other questions on the forms and have seen similar questions but no concrete answers I could follow.
I’ve taken the MRMAC reference design provided by AMD to work with internal / near-end PCS loopback on the VPK120, however I’m not managing to successfully to modify the design to test the external QSFP-DD loopback with MRMAC.
Following advice from a support question ( AMD Customer Community ), I’ve modified the MRMAC IP to the following:
MRMAC Config Preset: 2x50GE LAUI-2 Consortium Narrow
MRMAC Mode: MAC + PCS
MRMAC Site: MRMAC X0Y1
GT Type: GTM
GT RefCLK: 322.265625
I then set the following constraints to use GTM Bank 205 for QSFPDD-1 (following AMD Technical Information Portal and the schematic):
set_property LOC GTM_QUAD_X0Y3 [get_cells -hier -filter {name =~ */gt_quad_base*/inst/quad_inst}]
set_property LOC GTM_REFCLK_X0Y6 [get_cells -hier -filter {name =~ *_exdes/*_IBUFDS_GTE5_REFCLK0}]
##### GTM Bank 205
set_property PACKAGE_PIN Y45 [get_ports gt_ref_clk_p]
set_property PACKAGE_PIN AL52 [get_ports {gt_rxp_in[0]}]
I achieve timing, but flashing onto the FPGA with a ML4062-LB-112 dongle the GTs don’t lock. I am also changing the refclk using the VPK120 SCUI.
Any advice on how to modify the MRMAC reference design, or if there are any additional things to add, to achieve external loopback using either QSFP port would be very welcome. Cheers.