This material is intended to aid users in programming the Zynq7 FPGA inside a Red Pitaya multifunction equipment – based low cost electronic board with many components such as two core ARM processor, fast ADCs, fast DACs, USB, LAN, etc. In many respects Red Pitaya is similar to the Arduino or Rasbery Pi with large community of enthusiasts and increasing collection of open-source material. What makes Red Pitaya even better are two fast ADCs, two fast DACs and, most of all, the programmable logic or field-programmable-gate-array (FPGA). With on-chip FPGA Red Pitaya could be used for high performance computing, state-of-the-art measurement system, signal processing and much more. Having both linux-based processing system and programmable logic Red Pitaya is an ideal board for introduction to the FPGA programming and ultimately for building powerful professional and non-professional projects such as radar, radio systems, vector-network-analyzer, etc.
==== 1.1. Basics of Digital Systems ====
===== 1.1.1. Introduction =====
This will be a series of general topics about the concepts of digital systems and programmable logic. A digital system is a system made up by logic gates, which transforms logic input into a logic output with a logic function. Memories, processors, cellphones and all kind of electronics have digital circuits, logic gates are the building blocks of a digital system. They can be implemented with analog circuits and digital circuits, but with the advance of the semiconductor technology there are much more electronic circuits. These circuits are made up by transistors, MOSFETs, and passive components like resistors, capacitors and inductors.
An ASIC (Application Specific Integrated Circuits) is digital circuit that is on the vast majority of the electronic devices. The company does a project of a digital circuit and then fabricates thousands of chips to sell in the market. They are smaller, consumes low power, but the initial project costs a lot of money and you cannot change the circuit when it is already fabricated.
An FPGA (Field Programmable Gate Array) is an integrated circuit that can be programmed and reprogrammed in the field. It has many logic gates, registers, flip-flops and the user program it configuring the connections between them. The advantage of an FPGA is the versatility that it has for tests and for learning.
=====[1.1.2. Digital Information and Numerical Bases — Red Pitaya 0.97 documentation 1.1.2. Digital Information and Numerical Bases]=====
=====[1.1.3. Mathematical Operations with the Binary Base — Red Pitaya 0.97 documentation 1.1.3. Mathematical Operations with the Binary Base]=====
=====[1.1.4. Boolean Algebra — Red Pitaya 0.97 documentation 1.1.4. Boolean Algebra]=====
=====[1.1.5. Other Gates — Red Pitaya 0.97 documentation 1.1.5. Other Gates]=====
=====[1.1.6. Boolean Functions — Red Pitaya 0.97 documentation 1.1.6. Boolean Functions]=====
=====[1.1.7. Karnaugh Map — Red Pitaya 0.97 documentation 1.1.7. Karnaugh Map]=====
====1.2. Basics of Verilog FPGA programming language====
=====[1.2.1. FPGA and Red Pitaya — Red Pitaya 0.97 documentation 1.2.1. FPGA and Red Pitaya]=====
In a project of a digital system the developer studies a problem and builds a combination of logic gates, registers, flip-flops, and more complex blocks like RAM, ROM, processors, etc. Today with the advance of the technology we can implement the project with a FPGA (Field Programmable Gate Array). The FPGA is made with lots of logic blocks and each block contains logic gates, multiplexers, registers, etc. To implement the project the user of the FPGA has to make connections between these logic blocks and this is done with a HDL (Hardware Description Language).
Red Pitaya uses Verilog and System Verilog as a HDL. The Red Pitaya board has a programmable logic made by Xilinx and to write it to describe your digital system you must use the software Vivado. Vivado is used to write your digital system with a HDL and to implement your system in the programmable logic. The result of the implementation of a Vivado project is a file called bitstream that has an extension .bit, that has the information about the connections of logic blocks that will be used and the connections between them.
Every application of Red Pitaya (Osciloscope, Signal Generator, etc) uses a specific bitstream file, that implements the digital system needed for the application.
=====[1.2.2. Introduction — Red Pitaya 0.97 documentation 1.2.2. Introduction]=====
====== 126.96.36.199. Introduction ======
Verilog is a HDL, it is very similar to the C programming language and it was developed in 1985. Verilog became popular because it is easy to learn if you have some programming experience with C. With Verilog you can describe the system in a sequential or in a combinational way and the most popular tools that are used to develop digital systems support Verilog.
In Verilog the system is described with inputs, outputs and modules that implement some logic function. The system designer will implement modules and the software will optimize and implement the system to use less logic cells as possible, in Red Pitaya case the software used is Vivado. Modules can be implemented inside other modules, a module output can be another module input. A module is declared using the words ‘’‘module’’’ and ‘’‘endmodule’’’, the function, the inputs and outputs are declared inside it. Some characteristics of Verilog are:
- It is case sensitive, for example an input named ‘’‘adc_in’’’ is different from an input named ‘’‘Adc_in’’’.
- All statements of Verilog language, like ‘’‘module’’’, are in lowercase.
- The semicolon is used to end a line of code.
- Line comments are made with ‘’’// code’’’, and block comments with ‘’’/* code block */’’’.
=====[1.2.3. Values — Red Pitaya 0.97 documentation 1.2.3. Values]=====
=====[1.2.4. Operators — Red Pitaya 0.97 documentation 1.2.4. Operators]=====
=====[1.2.5. Assignments — Red Pitaya 0.97 documentation 1.2.5. Assignments]=====
Verilog HDL Basics - Altera
=====[1.2.6. Statements and Loops — Red Pitaya 0.97 documentation 1.2.6. Statements and Loops]=====
Behavioral statements are declared inside an ‘’‘always’’’ or ‘’‘initial’’’ block. There are three possible statements, ‘’‘if-else’’’ ‘’‘case’’’ and ‘’‘loop’’’.188.8.131.52. References
Verilog HDL Basics - Altera
=====[1.2.7. Tasks and Functions — Red Pitaya 0.97 documentation 1.2.7. Tasks and Functions]=====
=====1.3. Vivado FPGA programming environment=====
===== [1.3.1. Installation of Vivado — Red Pitaya 0.97 documentation 1.3.1. Installation of Vivado] =====
===== [1.3.2. Programming the FPGA — Red Pitaya 0.97 documentation 1.3.2. Programming the FPGA] =====
=====1.4. FPGA lessons=====
=====1.4.1. Project setup=====
*Windows 10 or Ubuntu 18.04
*RepPitaya ecosystem project
Xilinx SDK is available from Xilinx downloads page: Downloads
At this stage it is assumed that Red Pitaya is successfully connected the local network with an established ssh (or Putty) connection. If not, follow Red Pitaya’s official quick-start instructions.
For the FPGA development platform we will use Xilinx’s Vivado Design Suite with SDK. At the time of writing the latest version was Vivado 2020.1, however, other versions would also work. The Vivado Suite can be installed for free with WebPACK licence, which can be downloaded after registration from their webpage.
To install Vivado follow these steps:
#Register, download and install latest Vivado Design Suite with SDK.
#Obtain free WebPACK licence
To work with Vivado and its instruments in Windows we use TCL shell and Command prompt. Launch ‘’‘Vivado HLS 2020.1 Command Prompt’’’ Change to the folder with cloned RedPitaya project and launch the project generation.
======184.108.40.206. [220.127.116.11. Simple LED blinker — Red Pitaya 0.97 documentation Simple LED blinker]======
======18.104.22.168. [22.214.171.124. Knight Rider — Red Pitaya 0.97 documentation Knight Rider]======
======126.96.36.199. [188.8.131.52. Stopwatch — Red Pitaya 0.97 documentation Stopwatch]======
======184.108.40.206. [220.127.116.11. Frequency Counter — Red Pitaya 0.97 documentation Frequency Counter]======
======18.104.22.168. [22.214.171.124. Simple Calculator — Red Pitaya 0.97 documentation Simple Calculator]======
======126.96.36.199. [188.8.131.52. Moving average on Red Pitaya — Red Pitaya 0.97 documentation Moving average on Red Pitaya]======
======184.108.40.206. [220.127.116.11. VGA tutorial — Red Pitaya 0.97 documentation VGA tutorial]======
======18.104.22.168. [22.214.171.124. Ping pong — Red Pitaya 0.97 documentation Ping pong]======
======[LNIV Red Pitaya Laboratory for Integrated Circuit Design]======