I am designing LF passive RFID transponder chip for animal tagging applications (ISO 11784/11785) . The operating frequency is 134.2K hz . Basically the reader has 50 Ohm impedance and due to inductive coupling , the chip is powered on. For this purpose , I have to match the input impedance of chip ie 50 Ohms , this will produce 300mV at input of chip at 10cm distance (10dB power). My matching network should be as such to have an input impedance of 50 Ohm . So i am stuck at RF-DC part of this chip. It includes the matching network followed on by a dickson multiplier. The dickson multiplier gets , lets say , 300mV at input , and after 6-7 stages , it multiplies and provides 1V at output . But as soon as i connect some load (an LDO) to it , the voltages drop down , I dont have enought current at output of Dickson multiplier. Why is it happening ?
I am using TsmcN65 nm technology
Greetings,
We at DK usually deal with chips that others have designed, more so than designing them.
That said, how much current are you attempting to draw from this power system? Any high-impedance power source will show a high output when unloaded, that falls as current flow is increased. The multiplier stage will add some impedance of its own, and while I don’t consider myself much of an RF designer, I’d expect that placing a load on a power system being driven from a received signal would affect the impedance matching conditions compared to an unloaded state.
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