Thermocouple Pmod Controller (top level file): pmod_thermocouple.vhd (7.1 KB)
SPI Master (must be included in the project): spi_master.vhd (8.8 KB)
- VHDL source code of a streamlined interface to Digilent’s Thermocouple Pmod (PmodTC1)
- Continually outputs the latest thermocouple data, reference junction temperature data, and fault bits on parallel interfaces
- Handles SPI communication and all data retrieval from the Thermocouple Pmod
- Configurable system clock rate
This details a VHDL component that handles interfacing to the Digilent’s Thermocouple Pmod, shown in Figure 1. Figure 2 illustrates a typical example of this Thermocouple Pmod Controller integrated into a system. As shown, the Thermocouple Pmod Controller connects to the Pmod ports and executes transactions to secure thermocouple temperature data, internal junction temperature data, and fault bits. The data is then presented on simple parallel interfaces which can be connected to user logic or to output ports on the FPGA.
Figure 1. Digilent Thermocouple Pmod TC1
Figure 2. Example Implementation
The Thermocouple Pmod uses Maxim Integrated’s MAX31855 to digitize the signal from a K-type thermocouple and provide a reference junction temperature for compensation. The measured thermocouple temperature is 14 bits, with a 0.25ºC resolution. The reference junction temperature is 12 bits, with 0.0625ºC resolution.
The Thermocouple Pmod Controller consists primarily of a state machine and an SPI Master component.
The design uses the simple state machine depicted in Figure 3 to implement its operation. Upon start-up the component immediately enters the start state. It remains in this state for 300ms to ensure the Pmod has ample time to power-up and complete the first temperature conversion. It then proceeds to the get_data state, where it initiates an SPI transaction with the Pmod to retrieve the conversion results. Once the transaction begins, the component enters the pause state. Here, it outputs the received information on the tc_temp_data, junction_temp_data, and fault_bits ports when it becomes available. Once the 100ms conversion period has elapsed, the component returns to the get_data state to initiate the next data retrieval transaction. Although not shown in the state diagram, resetting the component at any time returns it to the start state.
Figure 3. State Diagram
The state machine controls an SPI Master component to communicate with the MAX31855 converter on the Pmod. The SPI Master is configured with CPOL = 0 and CPHA = 0, to meet the requirements of the MAX31855. Complete documentation for the SPI Master component is available here.
The clocking of this Thermocouple Pmod Controller is configured by assigning values to the GENERIC parameters clk_freq and spi_clk_div, defined in the ENTITY. The parameter clk_freq must be set to the frequency (in MHz) of the provided system clock clk. Equation 1 defines how spi_clk_div is calculated.
where fclk is the frequency of the provided system clock in MHz. The system clock is provided on the clk input port.
Equation 2 defines the SPI clock frequency fsclk that results.
This calculation keeps the SPI clock at or near the MAX31855’s maximum specified serial communication frequency of 5 MHz (without exceeding it).
Table 1 describes the Thermocouple Pmod Controller’s ports. Data formats and detailed descriptions of the outputs are described below.
Table 1. Port Descriptions
The tc_temp_data port outputs the 14-bit thermocouple temperature data. The data is formatted in 2’s compliment with a resolution of 0.25ºC per bit.
The junction_temp_data port outputs the 12-bit reference junction temperature data. The data is formatted in 2’s compliment with a resolution of 0.0625ºC per bit.
Table 2 defines the outputs on the fault_bits bus.
Table 2. Fault Bits
This Pmod has a 6-pin connector. Table 3 provides the pinout for this connector. The Thermocouple Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.
Table 3. TC1 Pmod Pinout and Connections to Thermocouple Pmod Controller
The reset_n input port must have a logic high for the Thermocouple Pmod Controller component to operate. A low logic level on this port asynchronously resets the component. During reset, the component aborts the current transaction with the Thermocouple Pmod and clears the tc_temp_data, junction_temp_data, and fault_bits outputs. Once released from reset, the Thermocouple Pmod Controller resumes operation.
This Thermocouple Pmod Controller is a programmable logic component that interfaces to Digilent’s Thermocouple (TC1) Pmod. It handles all communication with the TC1 Pmod to provide a continual stream of updated thermocouple temperature data, reference junction temperature data, and fault signals on parallel output ports.
Comments, feedback, and questions can be sent to firstname.lastname@example.org.