ZCU104 LVDS pins default configuration

Embedded Development Boards, Kits, Programmers
1

We did the following, yet these pins are inoperable.

In the following scenario, are pins E14 and E15 of a ZCU104 Zynq chip configured as inputs or outputs?

  • we built a bitstream for the PL section of the ZCU104

  • we used a constraints file from Xilinx - see attached file “zcu104_Rev1.0_U1_01302018.xdc”: it set a property for E4 and E15 to LVDS

  • we did not connect pins E14 or E15 in our PL design - see the attached IO placement report file “design_2_wrapper_io_placed.rpt”

  • we did not (as far as we know) specify anything else about pins E14 and E15

2

Hello,

I am checking on this now. Will let you know when I have an answer.

3

^ E14 and E15 should be in LVDS mode, with whatever default the constraints file had set.

Regards,

4

We also received this back from the Product Manger:

The code you write defines most pins as either in or out, very few are fixed types.
If these are pl side pins, and you are not driving or using them , you should have a message on the warnings saying they are unconnected , and as such they are defined as high impedance after configuration.

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