7-Segment Display Driver (top level file):
Version 1.1: seven_segments.vhd (5.0 KB)
Added generic parameter to configure 7-segment display polarity
Version 1.0: seven_segments_v1_0.vhd (4.4 KB)
Initial Public Release
Binary to BCD Converter (must be included in the project): binary_to_bcd.vhd (5.8 KB)
Binary to BCD Digit Converter (must be included in the project): binary_to_bcd_digit.vhd (3.2 KB)
BCD to 7-Segment Mapping (must be included in the project): bcd_to_7seg_display.vhd (2.0 KB)
- VHDL source code of a 7-segment display driver
- Displays a multiple digit integer on 7-segment displays
- Does not display leading zeros
- Configurable number of 7-segment displays
- Configurable range of input integer values to display
- Configurable 7-segment display polarity
This details a Multiple Digit 7-Segment Display Driver circuit for use in CPLDs and FPGAs, written in VHDL. The component reads in an integer from user logic and outputs the integer on the necessary number of 7-segment displays. For integers with fewer digits than the display width, no leading zeros are displayed. This component was designed using Quartus II, version 13.1.0. Resource requirements depend on the implementation. Figure 1 illustrates a typical example of the 7-segment display driver integrated into a system.
Figure 1. Example Implementation
Figure 2 illustrates the operations the component performs to display the input integer on the 7-segment displays.
Figure 2. Operations Performed
The component uses the Binary to BCD Converter available here to perform the binary to BCD conversion.
The component determines whether each BCD digit is a leading zero using OR logic. The results serve as address signals for a series of multiplexers, each of which passes the original value (not a leading zero) or sets the value to “1111” (if it is a leading zero). Figure 3 depicts the circuit.
Figure 3. Removing Leading Zeros
This approach works, because the BCD to 7-Segment mapping described in the next section blanks the 7-segment display when it receives a non-digit BCD value (i.e. value > “1001”).
The bcd_to_7seg_display.vhd file maps the BCD numbers to the 7-segment outputs as shown. These outputs assume a common anode 7-segment display configuration. A multiplexer in the seven_segments.vhd top level file selects whether these values or their inverse are sent to the output ports. The ss_polarity generic determines this selection as described in the “Parameter Generics” section below.
There are three generics in the component’s entity used to configure the component.
The generic digits sets the number of 7-segment displays that the component controls.
The generic bits is required to perform the internal binary to BCD conversion. This generic should be set to the maximum number of bits needed to represent the range of input integers in binary. This typically corresponds to the maximum number that can be displayed on the 7-segment displays. The maximum number of bits required to represent a specific number of digits is defined by equation 1.
The answer is always rounded up (e.g. 4 digits require 3.322*4 = 13.288, rounds up to 14 bits).
The generic ss_polarity sets the polarity of the output signals that drive the 7-segment displays. This generic should be set to ‘0’ if the 7-segment displays are common anode (low = on, high = off) and ‘1’ if the displays are common cathode (high = on, low = off).
Table 1 describes the 7-segment display driver’s ports.
Table 1. Port Descriptions
Figure 4 depicts an example timing diagram. In this example, the number of 7-segment displays is configured to 3, as indicated by the generic digits . The generic bits is set to 10, since it requires 10 bits to represent the maximum value that can be displayed on three 7-segment displays (see “Parameter Generics” section above). The generic ss_polarity is set to ‘0’, specifying common anode. To display a number, simply present the number on the number input port. Here, the number “89” is presented for display. Once the number is internally converted (which requires bits + 3 clock cycles), it is output to the 7-segments as shown. The leading zero is not enabled on the first digit, whose corresponding outputs are set to off: “1111111”. The following digit, “8” has every segment on: “0000000”, and the final digit “9” has only the ‘ e ’ segment off: “0000100”. Once the input number changes to “123”, the component again performs the necessary conversions and maps the result to the appropriate 7-segment outputs.
Figure 4. Example Timing Diagram
The reset_n input port must have a logic high for the 7-segment driver component to operate. A low logic level on this port asynchronously resets the component. During reset, the component will blank the 7-segment displays. Any internal conversion in progress is aborted. Once released from reset, the component immediately begins converting the number input signal and outputs the result on the 7-segment displays.
This multiple digit 7-segment driver is a flexible programmable logic component that displays multiple digit integers across an appropriate number of 7-segment displays. Leading zeros are not displayed. The number of 7-segment displays is configurable, allowing the user to set up the component for a desired range of input integer values. The 7-segment display polarity is also configurable.
7-Segment Displays Pmod Controller (VHDL) - This design uses the 7-Segment Display Driver for Multiple Digits component described on this page to interface an FPGA to a peripheral module board that has two 7-segment displays connected with shared data lines.
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