Alchitry Au FPGA Demo

Embedded Development Boards, Kits, Programmers
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The Alchitry Au FPGA is an excellent board that feaures the Xilinx Artix 7 XC7A35T-1C FPGA with over 33,000 logic cells and 256MB of DDR3 RAM, (Available in different Speed Grade, Temperature Range, and Operating Voltages)

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The Alchitry FPGA platform Au edition, offers a total of 102 Input/Output pins with 3.3V logic level, 20 of which can be switched to 1.8V logic level; Nine differential analog inputs; Eight general purpose LEDs; a 100MHz on-board clock that can be manipulated internally by the FPGA; a USB-C connector to configure and power the board; and a USB to serial interface for data transfer. All the Alchitry boards have full Lucid HDL support.

By adding stackable expansion boards similar to shields or HATs called “Elements,” the Alchitry Au FPGA is able to expand its own I/O hardware capabilities by adding prototyping spaces, buttons, LEDs, etc.

The following Lucid HDL was used for this demo,

module blinker (
    input clk,   // clock
    input rst,   // reset
    output blink // output to LED
) {
    dff counter[26](.clk(clk), .rst(rst))
    
    always {
        blink = counter.q[25]
        counter.d = counter.q + 1
    }
}

which is used in the alchitry_top module,

module alchitry_top (
    input clk,              // 100MHz clock
    input rst_n,            // reset button (active low)
    output led[8],          // 8 user controllable LEDs
    input usb_rx,           // USB->Serial input
    output usb_tx           // USB->Serial output
) {
    
    sig rst                 // reset signal
    
    .clk(clk) {
        // The reset conditioner is used to synchronize the reset signal to the FPGA
        // clock. This ensures the entire FPGA comes out of reset at the same time.
        reset_conditioner reset_cond
        
        .rst(rst) {
            blinker my_blinker
        }
    }
    
    always {
        reset_cond.in = ~rst_n     // input raw inverted reset signal
        rst = reset_cond.out       // conditioned reset
        
        led = 8x{my_blinker.blink} // blink LEDs
        
        usb_tx = usb_rx            // echo the serial data
    }
}

along with the corresponding alchitry.acf file,

STANDARD(LVCMOS33), SIDE(TOP) {
    pin clk CLOCK FREQUENCY(100MHz)

    pin rst_n RESET

    pin led[0] LED0
    pin led[1] LED1
    pin led[2] LED2
    pin led[3] LED3
    pin led[4] LED4
    pin led[5] LED5
    pin led[6] LED6
    pin led[7] LED7

    pin usb_rx USB_RX
    pin usb_tx USB_TX
}

The Lucid HDL blinks all LEDs in the main Alchitry Au FPGA board. The Alchitry IDE was used to develop and program this demo. The following video shows the Alchitry Au FPGA board demo,

This demo also echoes back via the USB serial terminal the characters sent from the host,

 usb_tx = usb_rx            // echo the serial data

this is shown in the next serial terminal, as the characters were typed, they were loopback to the user,

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The FPGA on the Alchitry Au has a built in 12-bit 1 MSPS A/D converter with 9 differential inputs broken out. Eight of these are shared with digital IO and one pair is a dedicated input. The following block diagram illustrates the internal ADC in the Xilinx Artix 7 XC7A35T-1C FPGA,

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The FPGA on the Alchitry Au itself already has quite a bit of plenty internal memory, but the FPGA on the Alchitry Au has a built in memory controller that is connected to a 256MB of DDR3 RAM on board for additional memory. The Alchitry Au FPGA is a powerful FPGA board in a very small form factor that can be used for many apllications and the Xilinx Artix 7 XC7A35T-1C FPGA are available at DigiKey.

Have a nice a day!

This article is available in spanish here.

Este artículo está disponible en español aquí.

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