In this article, the Alchitry FPGA V2 Br Breakout Board Connectivity Platform Evaluation Expansion Board for the Alchitry Au V2 FPGA will be explained in detail to answer possible questions and to facilitate the implementation of any circuit in this expansion board using the schematic. This platform was covered in a previous article.
The schematic diagram is shown below,
The relevant area for I/O ports available in the expansion board of the schematic is this one,
Bank B in the expansion board, corresponds to J11, J12, J13 and J14 (in schematic) for each vertical line as shown below,
Similarly for Bank A in the expansion board, corresponds to J7, J8, J9 and J10 (in schematic) for each vertical line as shown below,
Finally, for J15 and J16 in the schematic corresponds to the following Ctrl area in a vertical fashion as shown below,
The JTAG interface signals are TMS => 43, TCK => 45, TDI => 47, TDO => 49. This completes a detailed description to clarify any possible questions in relation to the way these I/O ports are available at the expansion board. The Alchitry Au V2 FPGA is a portable, expandable and powerful board and is available at DigiKey.
Have a great day!
This article is available in spanish here.
Este articulo esta disponible en espanol aqui.