Here in this article we will show a Moore Finite State Machine demo for the Alchitry Au V2 FPGA Development Board (Xilinx Artix 7)
The Alchitry Au V2 FPGA Development Board (Xilinx Artix 7) was covered previously in Part 1 and Part 2. This particular demo will use the Windows PowerShell to develop a Moore Finite State Machine outlined in the next diagram developed for a previous demo in the Lattice ICE40 FPGA Ultraplus Board,
Before we proceed with this article, the first step is to install Vivado in a Windows Computer. Then add these paths to the Windows Environment,
C:\AMDDesignTools\2025.2\Vivado\bin
C:\AMDDesignTools\2025.2\Vivado\doc\eng\man
The following demo will include the following files in the project directory of your choice,
build.tcl
program-board.tcl
build-program.tcl
constraints.xdc
top.sv
moore_fsm.sv
The System Verilog HDL for this finite state machine is called moore_fsm.sv where the state names where changed to ONE, TWO and THREE from (RED, BLUE, GREEN) for this demo (since this board has all green LEDs) as shown below,
`timescale 1ns / 1ps
//Digikey Coffee Cup SystemVerilog HDL Moore State Machine
module Moore(
input logic clk,
input logic reset,
input logic next,
output logic led2, led1, led0
);
typedef enum logic [1:0] {ONE, TWO, THREE} statetype;
statetype state, nextstate;
// state register
always_ff @(posedge clk, posedge reset)
if (reset)
state <= ONE;
else
state <= nextstate;
// next state logic
always_comb
case (state)
ONE: if (next) nextstate = TWO;
else nextstate = ONE;
TWO: if (next) nextstate = THREE;
else nextstate = TWO;
THREE: if (next) nextstate = ONE;
else nextstate = THREE;
default: nextstate = ONE;
endcase
// output logic
assign led0 = ~(state == ONE & state != TWO & state != THREE);
assign led1 = ~(state != ONE & state != TWO & state == THREE);
assign led2 = ~(state != ONE & state == TWO & state != THREE);
endmodule
The input that controls the state transitions is connected to the Reset button in the Alchitry Au V2 FPGA Development Board (Xilinx Artix 7). An auxiliary counter decreases the frequency of the clock for visualization purposes only, as shown in the project demo top.sv System Verilog HDL file,
//Digikey Coffee Cup SystemVerilog HDL Moore State Machine
module top(input rst_n, input clk, output[7:0] led);
Moore fsm_sm1(.clk(counter[23]),.reset(1'b0), .next(rst_n), .led2(led[2]), .led1(led[1]), .led0(led[0]));
//Auxiliary counter to divide the clock to be used in the Moore State Machine Demo
reg [23:0] counter;
initial begin
counter = 0;
end
always_ff @(posedge clk)
begin
counter <= counter + 1;
end
endmodule
Please include the following constraints.xdc file in the folder,
set_property PACKAGE_PIN N14 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN P6 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property PACKAGE_PIN K13 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN K12 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN L14 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN L13 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN M16 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN M14 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN M12 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN N16 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
Then we proceed to create the following batch file build.tcl for assembling this project from the Windows PowerShell,
# Digikey Coffee Cup SystemVerilog HDL Moore State Machine Batch File
# read design sources (add one line for each file)
read_verilog -sv "top.sv"
read_verilog -sv "moore_fsm.sv"
# read constraints
read_xdc "constraints.xdc"
# synth
synth_design -top "top" -part "xc7a35tftg256-3"
# place and route
opt_design
place_design
route_design
# write bitstream
write_bitstream -force "top.bit"
This file reads the System Verilog HDL files for the demo, the relevant constraints of the project, and it requests the synthesis process for the xc7a35tftg256-3 FPGA, performs the place and route and generates the bitstream called top.bit that will be used in the next step to program the platform.
To execute this build batch file please issue the following command to Vivado from the Windows PowerShell,
\project> vivado -mode batch -source build.tcl
This will take some time to process depending on the computer used. After this build process is completed, we are ready to program the Alchitry Au V2 FPGA Development Board (Xilinx Artix 7) with the following program-board.tcl file,
open_hw_manager
connect_hw_server
current_hw_target
open_hw_target
set_property PROGRAM.FILE top.bit [current_hw_device]
program_hw_devices [current_hw_device]
This file will be executed from the Windows PowerShell as follows,
\project> vivado -mode batch -source program-board.tcl
This will program the Alchitry Au V2 FPGA Development Board (Xilinx Artix 7).
Both of these files build.tcl and program-board.tcl can be merged on a single batch file that will automatically perform the build and program called build-program.tcl,
# Digikey Coffee Cup Build and Program Batch File
# read design sources (add one line for each file)
read_verilog -sv "top.sv"
read_verilog -sv "moore_fsm.sv"
# read constraints
read_xdc "constraints.xdc"
# synth
synth_design -top "top" -part "xc7a35tftg256-3"
# place and route
opt_design
place_design
route_design
# write bitstream
write_bitstream -force "top.bit"
# program
open_hw_manager
connect_hw_server
current_hw_target
open_hw_target
set_property PROGRAM.FILE top.bit [current_hw_device]
program_hw_devices [current_hw_device]
In order to execute this new unified batch file please issue the following command,
\project> vivado -mode batch -source build-program.tcl
The following video shows the Moore Finite State Machine in the Alchitry Au V2 FPGA green LEDs outputs being changed as the Reset button was pressed and released.
This completes the demo for the Moore Finite State Machine in the Alchitry Au V2 FPGA Development Board (Xilinx Artix 7).
The Alchitry Au V2 FPGA is a portable, expandable and powerful board and is available at DigiKey.
Have a great day!
This article is available in spanish here.
Este articulo esta disponible en espanol aqui.