The present demo will implement a basic counter in the Intel® Cyclone® 10 LP FPGA evaluation kit via the 2x20 GPIO header.
The low cost Intel® Cyclone® 10 LP Evaluation Kit provides a very easy-to-use platform for checking out the performance and characteristics of the Intel Cyclone 10 LP FPGA device. In a previous article, it was described how to implement a virtual JTAG interface in this Cyclone 10 LP FPGA board.
In this demo the following GPIO header will be used to output the signals from the counter.
The specific verilog HDL used in this demo is this one,
// Digikey Coffee Cup Counter for 2x20 GPIO header for Intel Cyclone 10 board
module counter (
input wire clk, // 50MHz input clock
output wire GPIO0, //GPIO0
output wire GPIO1, //GPIO1
output wire GPIO2, //GPIO2
output wire GPIO3, //GPIO3
output wire GPIO4, //GPIO4
output wire GPIO5, //GPIO5
output wire GPIO6, //GPIO6
output wire GPIO7, //GPIO7
output wire GPIO8, //GPIO8
output wire GPIO9 //GPIO9
);
reg [31:0] counter;
initial begin
counter = 0;
end
always @(posedge clk)
begin
counter <= counter + 1;
end
assign GPIO9 = counter[31];
assign GPIO8 = counter[30];
assign GPIO7 = counter[29];
assign GPIO6 = counter[28];
assign GPIO5 = counter[27];
assign GPIO4 = counter[26];
assign GPIO3 = counter[25];
assign GPIO2 = counter[24];
assign GPIO1 = counter[23];
assign GPIO0 = counter[22];
endmodule
Everyone knows, which is not the goal in this endeavor here, that there are GUI tools and paradigms out there that facilitate this assignment process, but is a good exercise to go thru your system, that is why we are going thru this manual process. The relevant diagram of this 2x20 GPIO port in the Intel® Cyclone® 10 LP FPGA evaluation kit is shown below,
The required I/O definitions to complete this demo are shown below,
set_location_assignment PIN_L13 -to GPIO0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0
set_location_assignment PIN_L16 -to GPIO1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1
set_location_assignment PIN_L15 -to GPIO2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO2
set_location_assignment PIN_K16 -to GPIO3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO3
set_location_assignment PIN_P16 -to GPIO4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO4
set_location_assignment PIN_R16 -to GPIO5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO5
set_location_assignment PIN_N16 -to GPIO6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO6
set_location_assignment PIN_N15 -to GPIO7
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO7
set_location_assignment PIN_N14 -to GPIO8
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO8
set_location_assignment PIN_P15 -to GPIO9
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO9
The Sparkfun Logic Analyzer was connected to verify the signals in the 2x20 GPIO header port as shown in the next picture,
The following Sparkfun Logic Analyzer capture confirms the proper operation of the demo as shown below,
The Intel® Cyclone® 10 LP FPGA evaluation kit is an excellent powerful platform for developing many applications and is available at DigiKey.
Have a great day!
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