Jitter


#1

Jitter is defined as:

  1. the short-term variations of a digital signal’s significant instants from their ideal positions in time.

  2. The deviation from the ideal timing of the event.

So, the term “jitter” describes timing errors within the system.

Clock jitter does not actually change the physical content of the information being transmitted, only the time at which it is delivered. Depending on circumstance, this may or my not affect the ultimate decoded output.

Jitter vs Wander

Timing variations are split into two categories called Jitter and Wander

Wander:

  • timing variations that occur slowly
  • it is jitter with a frequency of 0 to 10Hz — wander is usually caused by temperature variations.

JITTER:

  • Clock jitter can cause a number of undesired effects on the system, such as data corruption and AC timing violations.
  • Timing jitter has always degraded electrical systems, but the drive to higher data rates and lower logic swings has focused increasing interest and concern on its characterization.
  • Characterization is important to help define, identify and measure jitter. It is needed to set compliance standards and design specifications.

All circuits will have some wander and is not usually a cause for much concern.JITTER, on the other hand, causes many sleepless nights for many developers.

You may have heard of several types of jitter.
Periodic, Cycle to Cycle, Time interval, Deterministic, Random, Pattern dependant, Bounded, Sinusoidal and Gaussian however basically they all fall under two categories. Deterministic or Random

Deterministic

  • Sometimes called periodic jitter. It is jitter that repeats in a cyclic fashion. It is pattern-dependant and is typically caused by external deterministic noise sources coupling into the system, such as switching power-supply noise or a strong RF carrier. It can also be caused by an unstable clock–recovery PLL (phase locked loop).

  • Periodic jitter is difficult to reject, and in most cases, the clock source must be improved in order to eliminate tones caused by periodic jitter.

  • It is always bounded in amplitude and has specific causes.
    - Cross Talk
    - EMI
    - Switching power supply noise
    - Simultaneous switching outputs (SSO)
    - Device Function Dependency

Periodic


Looking at the 3 signals above.

  • The first is an ideal clock with no jitter.
  • The second signal is a clock that is being modulated.
  • The third shows the modulation function.

When the function is high, it is adding to the period length; when the function is low, it is subtracting from the period length of the clock. You can see that if you were to measure across the 11 periods, you would get the same measurement for both the ideal clock and the jittered clocks. This is why getting a measurement of jitter is so difficult, and takes special testing equipment to do it.

Random Jitter

Random jitter is timing noise that cannot be predicted. It has no discernable pattern. It will increase in time and is referred to as unbounded and will affect long term reliability.
  • Causes include:
    • Thermal vibrations (noise) of semiconductor crystal structures.
    • White Noise (Less than perfect valence electron mapping due to semi-regular doping density )
    • Process anomalies
    • Flicker Noise ( low frequency applications, normally found in resistors, diodes, transistors, and switches.

Measuring Clock Jitter

A true measure of clock jitter is the accurate position of clock edges over time. The most direct method of examining the placement of edges is by using an oscilloscope. Unfortunately, any jitter measured with a standard oscilloscope is due to trigger instability. As a result, direct waveform measurements using even a very good oscilloscope are not a valid measurement of jitter.

The use of a high performance, wide bandwidth oscilloscope with high-speed clock jitter analysis software, is essential to get a good measurement of clock jitter.

That is not to say that the oscilloscope can not be used to observe jitter.

In the waveform, its peak to peak value may be estimated by adjusting an oscilloscope to display one complete clock cycle. When the scope triggers on the first edge, the period jitter can be seen on the second edge.

Keep in mind that the measured jitter is always larger than the true jitter of the circuit as the measured jitter includes both the jitter of the oscillator and the oscilloscope.

(Left to Right) Low Jitter/High Quality, Medium, High Jitter/Low Quality

Commonly referred to as an “eye diagram” each graph is a cumulative graphical portrait of the edge placement due to noise or jitter. Ideally, sampling occurs at the center of the “eye”. As the edge jitter increases, the apparent eye begins to close.
The better quality the digital signal transmission, the more open white space there should be in the eye.

  • The width of the white space of the final eye diagram is called, simply enough, the eye width. If an eye diagram is composed of enough samples (millions and millions of three time period transitions), the eye width is a good measure of the amount of time, in any given time period, that the data lines are stable. This can give a good idea of how much setup time and hold-time is allowable.

  • The height of the white space of the final eye diagram is called the eye height. If an eye diagram is composed of enough samples (millions and millions of three time period transitions), the eye height can tell where the receiver’s VIH and VIL need to be to sample the data correctly.

Ideal Minimum Jitter Scope Screen Shot


Excessive Jitter Screen Shot

Ways to Reduce Jitter

  • A well filtered power supply.
    • The main factor that can contribute to clock jitter is the presence of significant voltage drops in a design’s power supply. The device power and the ground input pins should have proper routing on the pcb and maintain a stable device voltage at all times.
  • A well designed board layout.
    • Good layout is all about keeping noisy currents from cross-coupling to the clock and signal lines. Adequate single ground plane is needed to prevent ground bounce and spurious oscillations.
  • Careful clock selection in designing phase
  • Limit I/O and CPU activity on the device.
  • Provide a proper filtering for PLL power supply input pins
  • Provide a reference clock clear from frequency noise.
  • On systems where clock jitter is beyond the acceptable AC requirements of the system, add a series RC circuit (RXFC + CXFC) to the XFC pin to provide a PLL noise rejections, allowing quick recovery of PLL lock conditions for wider frequency bandwidth.

Conclusion

In conclusion, various methods are employed to generate clock frequencies. Time spent to determine system needs in the design phase will result in fewer problems and less time spent correcting them later on. It will also help determine a cost-effective approach for each application.