Microchip E-Bike Tech Q&A - How to Ensure Anti-Interference & Data Accuracy of Speed Acquisition?

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Q: If multi-level sampling of speed is required, how do you ensure proper anti-interference performance and data accuracy of speed acquisition?

A: Adopt high-order filtering algorithms or phase-locked loop (PLL) solutions .

Why Does Multi-Level Speed Sampling Cause Interference Issues?

Multi-level sampling (or multi-rate sampling) refers to the scenario where speed signals may be collected or processed at different frequencies in the same control system. In sensorless control, speed signals are estimated through motor models and observation algorithms, and they inherently superimpose interferences such as electrical noise, PWM ripples, and current sampling errors.

If these “noisy” speed estimation values are directly fed into the controller—especially in the low-frequency loops of multi-level sampling—noise will be amplified or accumulated, leading to unstable control.

Role of High-Order Filtering Algorithms

High-order filters (e.g., second-order low-pass filters, Kalman filters, sliding mode filters) can effectively suppress high-frequency noise while retaining the dynamic characteristics of speed.

Key points for filter design:

  • The cutoff frequency should be low enough to filter out PWM and high-frequency ripple noise.
  • The delay should be small enough to avoid introducing phase lag that makes the control system sluggish.

Anti-Interference Performance and Accuracy of PLL (Phase-Locked Loop) for Multi-Level Speed Sampling

The block diagram of a PLL (Phase-Locked Loop) typically includes three core modules: Phase Detector (PD), Loop Filter (LF), and Voltage-Controlled Oscillator (VCO). In some scenarios, a frequency divider or signal preprocessing unit may be added. Its core logic is to achieve accurate synchronization between the “input signal frequency/phase” and “output signal frequency/phase” through closed-loop feedback.

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Functions of PLL Modules

  • Phase Detector (PD): Compares the estimated rotor position with the phase of the observed voltage signal.
  • Loop Filter (LF): Acts as a low-pass filter to eliminate high-frequency noise.
  • Voltage-Controlled Oscillator (VCO) or Integrator: Adjusts the speed and position estimation based on the filtered output.

The core logic of the PLL (Phase-Locked Loop) is to achieve accurate synchronization between the “input signal frequency/phase” and “output signal frequency/phase” through closed-loop feedback.

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