Optimizing the Switching Power Supply Layout by Minimizing Hot Loop PCB ESRs and ESLs

Can you optimize the efficiency of a switching power supply? Sure—minimizing hot loop PCB ESRs and ESLs is an important method for optimizing efficiency. A hot loop PCB can significantly improve the power efficiency, lower the voltage ringing, and reduce the electromagnetic interference (EMI).

Hot Loop and PCB Layout Parasitic Parameters
In switching regulators currents are usually relatively high and rapidly switched. this creates a voltage offset on a certain parasitic trace inductance. Also, current can capacitively couple into adjacent circuit parts and increase the noise radiation of a power supply.

The hot loop of a switching-mode power converter involves rapidly switching currents and is defined as the critical high frequency (HF) AC current loop formed by the HF capacitor and adjacent power FETs. A poorly designed hot loop layout suffers from a high level of PCB parasitic parameters, including the ESL, ESR, and equivalent parallel capacitance (EPC), which have a significant impact on the power converter’s efficiency, switching performance, and EMI performance.


Figure 1. A buck converter with hot loop ESRs and ESLs. (Source: Analog Devices)

Step Down DC-DC Converter Example: LTM4638

Figure 1 shows a synchronous buck step-down DC-to-DC converter schematic.
The hot loop is formed by MOSFETs M1 and M2 and the decoupling capacitor CIN.
The switching actions of M1 and M2 cause HF di/dt and dv/dt noise. CIN provides a
low impedance path to bypass the HF noisy content. However, parasitic impedance
(ESRs, ESLs) exists within the components’ packages and along the hot loop PCB

An accurate extraction of the hot loop ESRs and ESLs helps to predict the switching
performance and improve the hot loop design. There are tools for users to extract the PCB parasitic parameters, such as Ansys Q3D, FastHenry/FastCap, StarRC, etc. Commercial tools like Ansys Q3D provide accurate simulation but are usually expensive. FastHenry/FastCap is a free tool based on partial element equivalent circuits (PEEC) numerical modeling and can provide flexible simulation through programming to explore different layout designs, though additional coding is required.

Hot Loop PCB ESR and ESL vs. Decoupling Capacitor Position
The LTM4638 is an integrated 20 VIN, 15 A step-down buck converter module in a tiny 6.25 mm × 6.25 mm × 5.02 mm BGA package which offers high power density, fast transient response, and high efficiency. This module integrates a HF ceramic capacitor Cin which can be placed at different positions on the board allowing 3 different configurations for hot loop.

The first one is the vertical Hot Loop 1 (Figure 2), where CIN1 is placed on the bottom layer just beneath the μModule regulator. The µModule VIN and GND BGA pins are connected to CIN1 directly through the vias. These connections provide the shortest hot loop path on the demo board.


The second hot loop is the vertical Hot Loop 2 (Figure 3), where CIN2 is still placed on the bottom layer, but moved to the side area of the μModule regulator. As a result, an extra PCB trace is added to the hot loop and larger ESL and ESR are expected compared to vertical Hot Loop 1.


The third hot loop option is the horizontal hot loop (Figure 4), where CIN3 is placed on the top layer close to the μModule regulator. The µModule VIN and GND pins are connected to CIN3 through the top layer copper without going through vias. Nevertheless, the VIN copper width on the top layer is limited by the other pinout, resulting in an increased loop impedance compared to that of vertical Hot Loop 1.



To experimentally verify the ESRs and ESLs in different hot loops, the demo board
efficiency and VIN AC ripple at 12 V to 1 V CCM operation are tested. Theoretically, a
lower ESR leads to higher efficiency, and smaller ESL results in higher VSW ringing frequency and lower VIN ripple magnitude. Figure 5a shows the measured efficiency.
The vertical Hot Loop 1 gives the highest efficiency that corresponds to the lowest ESR. The loss difference between the horizontal hot loop and vertical Hot Loop 1 is also calculated based on the extracted ESRs, which is consistent with the testing result as shown in Figure 5b. The VIN HF ripple waveforms in Figure 5c are tested crossing IN. The horizontal hot loop has a higher VIN ripple magnitude and a lower ringing frequency, thus validating the higher loop ESL compared to the vertical Hot Loop 1. Also, because of the higher loop ESR, the VIN ripple in the horizontal hot loop damps faster than in the vertical Hot Loop 1. Furthermore, a lower VIN ripple reduces EMI and allows a smaller EMI filter size.

Hot Loop PCB ESR and ESL vs. MOSFETs Size and Position
For a discrete design, the placement and package size of power FETs also have a
significant impact on hot loop ESRs and ESLs. Cases (a) to (c) present three popular power FET placements with 5 mm × 6 mm MOSFETs. The physical length of the hot loop determines the parasitic impedance. Hence, both 90˚ shape placement in Case (b) and 180˚ shape device placement in Case (c) result in 60% ESR reduction and 80% ESL reduction because of the shorter loop paths compared to those in Case (a). Since a 90˚ shape placement shows the benefit, several more cases are investigated based on Case (b) to further reduce the loop ESR and ESL.

Figure 6. Hot loop PCB models: (a) 5 mm × 6 mm MOSFETs in straight placement; (b) 5 mm × 6 mm MOSFETs in 90˚ shape placement; (c) 5 mm × 6 mm MOSFETs in 180˚ shape placement

In Case (d), a 5 mm × 6 mm MOSFET is replaced with two 3.3 mm × 3.3 mm MOSFETs in parallel. The loop length is further shortened thanks to the smaller MOSFETs footprint, leading to 7% reduction of the loop impedance. In Case (e), when a ground layer is placed under the hot loop layer, the hot loop ESR and ESL are further decreased by 2% compared to Case (d). The reason is that eddy current is generated on the ground layer, which induces the opposite magnetic field and equivalently reduces the loop impedance. In Case (f), another hot loop layer is constructed as the bottom layer. If two paralleled MOSFETs are symmetrically placed on the top layer and bottom layer and connected through vias, the hot loop PCB ESR and ESL reduction are more obvious because of the paralleled impedance. Therefore, smaller sized devices with symmetrical 90˚ shape or 180˚ shape placement on top and bottom layers lead to the lowest PCB ESR and ESL.

Figure 6. (d) two-parallel 3.3 mm × 3.3 mm MOSFETs in 90˚ shape placement; (e) two-parallel 3.3 mm × 3.3 mm MOSFETs in 90˚ shape placement with ground layer; (f) symmetrical 3.3 mm × 3.3 mm MOSFETs on top and bottom layers in 90˚ shape placement.


Figure 7. (a) LT8390/ DC2825A hot loop with straight MOSFETs placement; (b) LT8392 / DC2626A hot loop with 90˚ MOSFETs placement; (c) VIN ripple waveforms at M1 turn-on.



Figure 8. Hot loop PCB models with (a) five GND vias placed close to CIN and M2; (b) 14 GND vias placed between CIN and M2; (c) 6 more vias placed on GND based on (b); (d) nine more vias placed on GND area based on (c).

Hot Loop PCB ESR and ESL vs. Via Placement
Hot Loop PCB ESR and ESL vs. Via Placement. The vias placement in the hot loop also has a critical impact on the loop ESR and ESL. As shown in Figure 8, the hot loop with a two-layer PCB structure and straight power FETs placement is modeled. The FETs are placed on the top layer and the second layer is a ground plane. The parasitic impedance Z2 between CIN GND pad and M2 source pad is part of the hot loop and is studied as an example. Z2 is extracted from FastHenry. Table 3 summarizes and compares the simulated ESR2 and ESL2 with different via placements.

In general, adding more vias reduces the PCB parasitic impedance. However, the reduction of ESR2 and ESL2 is not linearly proportional to the number of vias. The vias close to the terminal pads give the most obvious reduction in PCB ESR and ESL. Therefore, for hot loop layout design, several critical vias must be placed close to the pads of CIN and MOSFETs to minimize the HF loop impedance.


The reduction of a hot loop’s parasitic parameters can help improve the power efficiency, lower voltage ringing, and reduce the EMI. To minimize the PCB parasitic parameters, hot loop layout designs with different decoupling capacitor positions, MOSFET sizes and positions, and via placements were studied and compared. A shorter hot loop path, smaller sized MOSFETs, symmetrical 90˚ shape and 180˚ shape MOSFETs placements, and vias close to the key components contribute to the lowest hot loop PCB ESR and ESL.