Hello, I am trying to find out how to drive the Meanwell NLDD-1400H pulse width modulation (PWM) pin and the datasheet is not clear on how. I have tried to contact Meanwell but no reply.
The datasheet says: H: >2.5~5VDC or open circuit and L: <0.8VDC or short. It sounds there is an internal pull-up resistor for an open drain driving circuit, but, it also shows a voltage driving range hence push-pull circuit. I am at a loss as to what drive circuit to use, since I do not want to use a push-pull driver from 3.3V to 0V if there is an internal resistor to 5V. Internet search has not found anything, any help would be appreciated.
Thanks,
-Erik
erik.ingermann
Thank you for contacting DigiKey , PWM is another circuit that turns the voltage on and off for dimming the led output of the power supply , If you Google How to use pwm to control led there is a lot of info for this .
Thanks Craig
Hi erik.ingermann,
The fact that you can leave it open means that it has an internal pull-up. So, any typical 3.3V to 5V I/O pin will work fine.
Here’s a crude schematic of what I think it has inside:
Note that a logic low or short pulls the internal logic low. A value of 2.5V or greater will be recognized by the gate as a logic high, so your 3.3V PWM will work just fine. The only stipulation is that your I/O pin should be able to sink at least 2mA, as specified here:
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Thanks David, I was certain there was an internal pull-up, but that makes me think the PWM signal should be driven with an open drain driver and not a push-pull driver. If I use a push-pull (3.3V GPIO) I am worried about damaging the driver by sinking current from the GPIO through the internal resistor to the 5V rail. Thanks for pointing out the 2mA sink, I did not see that note my GPIO could easily sink that.
Thanks, but I have designed PWM circuits before what I was hoping was that Digikey had more information on exactly how Meanwell recommend driving the signal since they seem to indicate that it is an open drain design yet they also mention voltage drive levels for a push-pull type driver. Usually there is an example application design in the datasheet, but the Meanwell datasheet does not have that.
Hi erik.ingermann,
I have been trying to find any more info on this from MeanWell, but have not been successful thus far.
Assuming I have the internal schematic right, which is certainly not guaranteed, then the internal pull-up resistor ought to be >= 2.5k Ohms (5V / 2mA). If so, then, using a push-pull 3.3V PWM driver, it would need to sink no more than 0.7mA when high [(5V-3.3V) / 2.5kΩ] and 2mA when low. You’d have to check the specs on your PWM driver to verify whether it could handle that. Of course, using an external BJT or FET for an open-collector / open drain configuration would remove any worries, at the expense of a few additional parts and extra real-estate.
I’ll continue to look into this to see if there is any more definitive information on the matter.
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That sounds an awful lot like a description of typical TTL logic thresholds…
If one’s interested in understanding what potential that input is pulled to internally, the quickest way to find out would probably be to just power up a sample specimen, grab a voltmeter, and measure it.
Since TTL inputs float high, it’s possible to drive them with either an open-collector or push-pull output. Connecting a push-pull 3.3V output to a 5V TTL input can be expected to result in some flow of current from the 5V source, through the pull-up resistance, through the internal diode on the 3.3V output pin and into the 3.3V supply network.
Is that a problem? Maybe. Maybe not.
So long as one can assure that this current flow into the 3.3v output pin under output-high conditions doesn’t pull the 3.3v rail out of spec and that there aren’t issues with power sequencing (lots of LDOs don’t like to be reverse biased for example…) the arrangement can work.
And if that “so long as (…)” condition is violated? Expect the magic smoke to come out.
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Great info David, and thanks for your help! Since I am not completely certain I will probably go with the external FET design via an opto isolator (PC817). Someone had done this circuit on a Meanwell power supply with PWM, and I am hoping they are using the same PWM circuit as in their power supplies. I am driving this with a tiny ESP32C3 and I guess I would rather error on the safe side.
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That certainly should work, and remove any worries.
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Very good insight Rick. Since this is being driven my a tiny ESP32C3 I am nervous about damaging the ESP’s driver, e.g., MTTF, smoke, etc… I mentioned to David that I will most likely just use an OD/OC circuit via an opto isolator. My concern with this was that I wanted to switch the PWM signal at around 1KHz, so I am hoping the internal pull-up and capacitance are not going to interfere, i.e., not able to reach full swing. If not, I guess I will just reduce the switching rate. Thanks again for all the help!
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Well, if you have need to isolate the power domains of controller/controlled device, that’s a different kettle of fish altogether.
If not, using an opto would seem a rather clumsy and expensive degree of overkill when a person could just use a small transistor instead.
You are absolutely correct, Rick, but I only need about 12 of these and the opto’s are $0.48ea. Since someone has already used an ESP32 with an opto to drive the PWM signal on a Meanwell power supply (not a CC like this one) I was going to leverage their design. In a production scenario I would definitely go with your idea. Thanks for the input!
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In the event anyone is interested, I did get a reply from Meanwell: “The MCU of the NLDD does have a pull-up circuit to keep it ON when DIM pin is open, so you might want to choose open drain.” Not really a huge amount of info but at least validating the open drain idea.
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