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Hi all,
We are developing a system based on one of the SAMA5 System-In-Package devices, the SAMA5D27-LD2G, which incorporates a 2Gbit LPDDR2 RAM within the same epoxy package as the MPU. Unfortunately I have not been able to make the SAMA5’s DDR-controller configure correctly and write/read data from the RAM - pretty fundamental in order to run Linux on it! We did initial development using the SAMA5D27-SOM1-EK (which has non-low-power DDR2 RAM), and had no such problems.
I’ve opened a support case with Microchip, but after an initial flurry of activity I’ve now been waiting nearly a week now for a reply from them. So…
If anyone has a working SAMA5 system with LPDDR2 RAM (either in-package or external), I’d love to hear from you!
Thanks Robert, yes, AT91Bootstrap was where we started. But both it, and the Atmel Software Pack (https://github.com/atmelcorp/atmel-software-package) have LPDDR2-initialisation code that doesn’t work , at least on our prototype boards. If only there was a SAMA5 evaluation board with LPDDRAM!
Turns out Microchip do have an evaluation board for this SIP device (photo here), but I guess it hasn’t been released yet. Apparently my code runs OK on this board when they debug using IAR Embedded Workbench - I’ve asked for a binary I can test on our hardware…
Believe we have found the problem - our prototype design lacks a DDR_VREF signal!
The SAMA5D2-series and SAMA5D2-SIP datasheets DS60001476C and DS60001484B do not properly describe this signal. I have notified Microchip via the support case we already have open, hopefully the datasheets will be revised in due course.
I don’t have any info regarding confirmation of the fix, but I see that they have recommendations for the schematic when using external LPDDR2 with the non-SIP version on page 38 of application note AN2717 - SAMA5D2 Dynamic Memory Implementation Guidelines.
They show DDR_VREF as a voltage derived from VDD_DRAM divided by two (via two 2.2K resistors and some caps) and fed to DDR_VREFB0 and DDR_VREFCM of the SAMA5. I see that the SIP version brings out the DDR_VREF pins on M12 and J10, so it would seem logical that one needs to do the same for the SIP package as well. This voltage at the midpoint of the LPDDR2 supply rail would ensure that both the RAM and the microprocessor are communicating with the same voltage levels.
