SuperCap balancing

Hello,

i am looking for a solution for balancing supercaps in 3s2p configuration which is not very expensive and has the least BOM.
Currently using this

Hi @anishkgt,

I would recommend using Advanced Linear Devices Inc.'s supercapacitor auto balancing MOSFET arrays, such as the ALD810026SCL or ALD810027SCL.

These are MOSFET arrays which have carefully tuned threshold values which are to be connected in parallel with each supercapacitor. When the voltage across each capacitor is below the threshold value, the MOSFETs conduct only nanoamps of current, but their conduction grows exponentially as the capacitor voltage increases, thereby keeping the cells balanced.

In addition to the integrated circuit packages, we also carry boards, either unpopulated or populated with the IC’s already soldered on, for evaluation purposes, such as those linked here:

If you find that they do not conduct enough current due to very high capacitor leakage currents, or that you need to balance very quickly due to high charge currents, one can add a few external components to increase the balancing current dramatically. The following boards can be used to test such circuits.

High-balancing current evaluation boards:

1 Like

I had earlier come across the SABMOSFETs but was a bit skeptical. It was because of how well it would work for my application.

My Vin (earlier 8.1v) should now be 2.7v. These are in 3s2p configuration so the total capacitance would be 207F. From the supercap datasheet the leakage current is typically 0.45mA.How does this trigger the MOSFETs ? For example if, in the attached schematic diagram that you have attached the said leakage current starts to flow. I am guess this would trigger M1 ? and the source would start to conduct and M2 would be triggered ? Would it go on ? what happens when charging starts how does it start the balancing ?

I cam across this AN. Not sure if this would work with a 3s2p configuration.
sabfet_11106.0.pdf (100.0 KB)

That’s essentially how you would connect it. In terms of functionality, these work based upon the voltage the MOSFETs “see” between the gate and the source. The FETs are voltage controlled devices. As the voltage approaches the “threshold gate voltage” of each FET, they start to turn on and allow current to flow through themselves. Below this threshold, they conduct only nanoamps; thus they are essentially an open circuit.

image

Notice that in the schematic you referenced, pin 3 (the gate of M1) is connected to the “+” side of C1 and pin 4 (source of M1) is connected to the “-” side of C1. This means that the gate to source voltage is the same as the voltage across each capacitor. When charging the capacitor string, the voltages of each capacitor will begin to rise, but they will rise at different rates, based on variations in leakage current and other factors. This is why balancing circuits are necessary. If not employed, some capacitors may exceed rated voltage before others reach the rated voltage.

With the special ALD MOSFET array, when the voltage of any capacitor in the series approaches the threshold voltage of the FET connected in parallel with that particular capacitor, the FET begins to conduct current around that capacitor and pass that down to the next capacitor in the series. The higher the voltage on any capacitor, the more current it conducts, and that current grows exponentially with increased voltage. The effect is that all of the capacitors can reach their optimal voltage value with no overcharging of any one capacitor and with the least amount of balancing current.

If you have plenty of excess power available you could employ a simpler balancing circuit by just placing a resistor in parallel with each capacitor. To properly balance them with this method, the resistor must be sized to allow at least 10x the current through them as there is leakage current through the capacitors. In your capacitors, the leakage is specified to be as high as 750uA per cap, so the resistors would have to be no more than 180 Ohms for two caps in parallel {2.7V / (10 x 2 x 750uA) = 180 Ohms}. They could be physically, very small, as power requirements would only be about 40mW. However, with this method, you would have a continuous current draw of at least 15mA even when the capacitors were fully charged in order to maintain the balance.

If you are considering the ALD chips, we will need to figure out which threshold voltage best matches the requirements of your capacitors. Also, for higher system reliability, you might want to consider lowering your charge voltage by a tenth of a volt or so per cap, to give yourself a little margin for short-term overvoltage conditions which can arise under real-world conditions. This would mean dropping your overall voltage down to 7.8V from 8.1V. This will, of course, lower your reserve total energy storage slightly, but would likely add reliability and life expectancy.

I will take a closer look at the specs of your cap and see which threshold voltage makes the most sense in your particular case.

1 Like

Since the charge current is limited to 10A i would go with an SMPS salvaged from a desktop CPU. Most of them are rated 12v at 12-13A.

yes lower voltage increases life of a cap but am bit worried of the stored charge and how much time it would take to charge ? at 7.8 it should fairly quicker than 8.1v. Will have to get a prototype done to estimate that.

So talking about the leakage current is it current that leaks out when idle ? if am not wrong current moves from (-) terminal to (+) so would i see an LED glow if it was reverse biased ? or are those current in the nA range to notice.

Regarding charge time, it would take about 4% less time to charge to 7.8V vs. 8.1V with a constant current charger, but the total energy stored would be about 7% lower, since energy is a function of voltage squared.

Regarding leakage current, direction of current depends on which school you go to. Technically, electrons flow from negative to positive, but at least in the US, the convention is that “current” flows from positive to negative. Yes, the leakage current is current that leaks through a capacitor, whether idle or being charged. The higher the voltage a capacitor is charged to, the greater the leakage tends to be. The net result is that over time, the voltage across the terminals of a capacitor will drop because of the lost charge.

Actually, with supercaps, it’s a bit more complicated than that. Electrically, they behave more like a whole bunch (thousands) of capacitors in parallel, each with their own series resistance, and the values of the resistances and capacitances and their resulting RC time constants vary over several orders of magnitude. The net result of this is that when you stop charging them, the charge stored in the more fully charged caps within the device slowly feed charge to the less charged ones. This causes the overall externally measured voltage to drop as the charge re-distributes. Because of this behavior, the leakage current will seem greater than it actually is, because much of the charge is being redistributed rather than lost.

The typical means of calculating a capacitor’s leakage current is not to directly measure it, but rather calculate it based on voltage drop across the capacitor over a given period of time. Because of the very non-ideal behavior of these devices, the true long-term leakage current is usually much lower than what is calculated. It really depends on the application as to whether one should use the higher or lower leakage current calculation. If the caps are going to be charged and discharged frequently, then the higher value is more relevant because the effect on sagging voltage after charging is greater. The longer one charges them, the less voltage droop will be observed.

1 Like

Hi @anishkgt,

I have looked through the specs of some of the ALD FET arrays, and based on the leakage current of the capacitors you are using, of up to 1.5mA (2 x 750uA for two in parallel), I don’t know if you can use the basic FET array alone and still bypass enough current to overcome that. If you use two of them in parallel for each capacitor pair, you might be able to, but it may not be ideal.

If you go this way, you should probably use one ALD910021SALI for each capacitor pair with the two FETs connected in parallel for twice the bypass current and plan on charging to no more than 2.6V (7.8V for the whole stack). At 2.6V and in parallel, they will have a continuous current in the neighborhood of 2mA, which is borderline for maintaining balance compared to the possible leakage current of the caps.

For high leakage caps in the 1mA range and up like you have, you may be better off using the amplified version of the circuit, like they use on their SABMBOVP227 reference board. By adding 2 resistors and one small P-channel MOSFET to each node in this circuit, it transitions from very low current conduction to very high current conduction over a very small voltage range. This allows one to charge the capacitors to a higher voltage level but still control overcharging much more effectively by shunting almost all excess charge around the cap once it reaches its threshold voltage. This effectively clamps the voltage at a specific voltage such as 2.7V for the SABMBOVP227.

1 Like

Hi @David_1528,

Appreciate your time for this. I would have to look at this once i have the boards populated and tested with the comparator and the SABFETS. Its a compromise between the life of the caps and energy storage.

Not sure if this would help, there are a couple of designs for Engineers once registered at ALD. It was where i got the previous document. They had one with parallel arrays as well, did not understand it.

Here is a table to select a SABmosfet if some one would need it.
ALD8100xxTable.pdf (389.9 KB)

In the datasheet of ALD810028 it says

Each SAB MOSFET features a precision gate threshold voltage in the Vt mode, which is 2.80V when the gate-drain source terminals(VGS = VDS) are connected together at a drain-source current of IDS(ON) = 1μA. In this mode, input voltage VIN = VGS = VDS. Different VIN produces an Output Current IOUT = IDS(ON) characteristic and results in an effective variable resistor that varies in value exponentially with VIN. This VIN, when connected across each super capacitor in a series, balances each super capacitor to within its voltage and current limits.

The “IDS (ON) = 1uA” means the max current from drain-source should be no more than 1uA. So how is it calculated in my application of 3s2p ? Leakage current of one of the MAXWELL cap alone is .75mA which is way more than the rated current of 1uA.

Yes, I was using that table to try to determine which one would be the most appropriate. The chart shows how much current each part number will conduct (pass through its MOSFET) at a given voltage. As higher voltages are applied to the gate of the FET, more current it will pass. The part numbers are defined by what magnitude of gate voltage will cause 1uA of current to flow through the FET. They call this voltage the threshold voltage, Vt. The chart also shows how much more current will flow at higher voltages.

In the case of your caps in parallel, the leakage is as much as 1.5mA at 2.7V. You will want a SABmosfet which will pass more than that much current at no more than the voltage to which you intend to charge them in order to maintain balance. The higher the FET current, the better job it will do in maintaining the balance. You can parallel the FETs in the SABmosfet package to double the current at any given voltage, since you would then have two FETs conducting rather than one.

From the table you mentioned, one can see that the ALD810019 would conduct 1mA at 2.42V and 3mA at 2.72V. If you use two FETs in parallel, you can double those numbers to 2mA and 6mA, respectively. This would give reasonably good balancing under moderate charge/discharge conditions, but it would mean drawing at least that much current continuously, even when the caps were fully charged.

However, depending on the nature of your charge/discharge characteristics and how much balancing current you can tolerate, you may find that you need a higher current gain-to-voltage ratio. That is why I mentioned the SABMBOVP227. This part will conduct about 1mA at 2.7V, but at 2.6V it will only conduct around 0.07uA (very low current), and, conversely, at 2.73V it will conduct around 100mA (very high current). This will very effectively maintain the voltage of each cap at no more than about 2.7V.

Can you explain how you came across the the 1.5mA figure.

Since the max leakage for each cap was 750uA, two in parallel would be 1500uA, or 1.5mA.

Where can i get a schematic for the SABMBOVP227 PCB ? The one that comes with the PCB is not clear.

Let me see if i have got this correct.

Deciding on which IC to chose is based on the leakage current of the capacitor(s) this IC is in parallel with. So in a 3s2p we have 3 PAIRS of caps. That would be 0.75mA (leakage current of one cap mentioned in datasheet) x 2 = 1.5mA. Otherwise 1500uA because the IC datasheet references the reading in micro amps.

So in an application dealing with super-capacitors or energy storage devices we would need the MOSFET to have maximum resistance at lower voltage and start to conduct when the voltage reaches closer to 2.7v and hence conduct with least resistance when the voltage reaches 2.7v. In post#12 (if i have understood the table) the table says, the Vth for ALD810019 is 1.9v. This would mean that at 1.9v at the gate, the MOSFET would conduct (or begin conducting) 1uA and as this 1.9v (Vgs) starts to increase so does the Ids (current flowing from Drain to Source) there by maintaining a constant voltage across its parallel capacitor.

Now what does the resistors do here ? Dissipate the extra current as heat ? if yes then they would be in placed in parallel with drain and source of the conducting drain and source ?

Sorry about the long write-up, just making sure i understand the working of the IC before i go ahead with implementation.

Would a P-MOSFET like the BSS215P be an ideal match here ? From the SABMBOVP2XX application note, there are two gate resistors for the P-MOSFETs. Would a 450R be ok here ? At 450R and with a Drain-Source voltage of 1.9v would hit the Vgs (-1.2v) of the P-MOSFET.

Hi @anishkgt,

You have the basic idea right for the ALD810019. However, for the circuit with added transistor and resistors, the current gain is much more dramatic. With that circuit, you can move up to a 2.7V threshold SABmosfet. I didn’t find a schematic with specific values, but by using what was given in the datasheet plus examining the image of the board, I have an idea of what is used.

Here is the schematic from the datasheet for one capacitor with the optional resistors removed for clarity:

image

In this circuit, M1 is used to turn on Q1. Rx2 pulls the gate voltage of Q1 high, thereby turning it off when M1 is not conducting. As M1 begins to conduct, current is drawn through Rx2 and the voltage at the gate of Q1 begins to drop, causing it to begin to conduct. By scaling Rx2 appropriately, there won’t be much of a voltage drop at the gate of Q1 until 1uA is drawn through Rx2. This occurs when the voltage across the capacitor reaches the Vth value of M1. As Q1 begins to turn on, the current will rapidly increase through Q1 and Rp1. Rp1 is scaled so as to allow around 100mA to conduct when C1 is a little above the threshold voltage, when Q1 is fully enhanced and only dropping hundredths of a volt.


From the image on our website, Rp1 is a 24 Ohm 1W resistor and it looks like Rx2 is a 1.8M Ohm resistor. I could not identify Q1, but I think the BSS215P you mention would probably work fine, as it has a relatively low Vgs-th and reasonably low Rds-on. Something like the DMG2301LK-7 is another option with a few additional benefits, as it has a lower Rds-on and can handle more power, which gives it a bit more design margin. You may have to play a round a little with the value of Rx2 to get the optimal turn-on characteristic, but 1.8M Ohm is probably a good starting point.

1 Like

hi @David_1528,
Thank you for the reply.

Yes i had figured it out after a while. So Rp1 has to be scaled to keep the voltage at C1 at 2.7, is that correct ? I’ve managed to get a schematic done. When laying out the board should the resistors be closer to gate or is it ok have these power resistors a bit away and grouped together as they may dissipate little heat. So with the additional P-MOSFET and power resistors can i use the ALD810027 or the ALD810028SCL? CD_Spotwelder_ALD801xxx.pdf (97.9 KB)